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1 dsc-6157/2 december 2003 idt72t55248 idt72t55258 idt72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8,192 x 40 x 4 16,384 x 40 x 4 32,768 x 40 x 4 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are registered trademarks of integrated device technology, inc commercial and industrial temperature ranges 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 ff 0/ ir 0 paf 0 ff 1/ ir 1 paf 1 ff 2 / ir 2 paf 2 ff 3/ ir 3 paf 3 wen 0 wcs 0 wen 1 wcs 1 wen 2 wcs 2 wen 3 wcs 3 wclk0 wclk1 wclk2 wclk3 10 10 10 10 d[9:0] d[19:10] d[29:20] d[39:30] ef 0/ or 0 pae 0 ef 1/ or 1 pae 1 ef 2/ or 2 pae 2 ef 3/ or 3 pae 3 cef / cor q[39:0] x10,x20,x40 ren 0 rcs 0 rclk0 oe 0 read control queue 0 queue 1 queue 2 queue 3 os[1:0] read port flag outputs write port flag outputs mux mode 6157 drw01 queue 0 data in queue 1 data in queue 2 data in queue 3 data in data out 2 features ? ? ? ? ? choose from among the following memory organizations: idt72t55248 - 8,192 words, 40-bits/word maximum, 4 sequential queues total idt72t55258 - 16,384 words, 40-bits/word maximum, 4 sequential queues total idt72t55268 - 32,768 words, 40-bits/word maximum, 4 sequential queues total ? ? ? ? ? user selectable mux / demux / broadcast write modes ? ? ? ? ? mux mode offers 4:1 architecture - five discrete clock domains, four write clocks and one read clock - four separate write ports, writes data to four independent queues - one single read port, capable of reading from any four queues - selectable single or double data rate (sdr/ddr) on read and write ports - 10-bit wide write ports in single data rate, doubles internally in double data rate - 40-bit wide read port, doubles internally in double data rate, selectable between the four independent queues - bus matching on the read port x10/x20/x40 (sdr/ddr) - fully independent status flags for every queue - composite empty/output ready flag monitors currently selected queue - dedicated partial reset for every queue ? ? ? ? ? demux mode offers 1:4 architecture - five discrete clock domains, one write clock and four read clocks - four separate read ports, read data from four independent queues - one single write port, capable of writing to any four queues - selectable single or double data rate on read and write ports - 10-bit wide read ports in single data rate, doubles internally in double data rate - 40-bit wide write port, doubles internally in double data rate, selectable between the four independent queues - bus matching on the write port x10/x20/x40 (sdr/ddr) - fully independent status flags for every queue - composite full/input ready flag monitors currently selected queue - dedicated partial reset for every queue ? ? ? ? ? broadcast write mode offers, 1:4 architecture (with simultaneous writes to all queues) - five discrete clock domains, one write clock and four read clocks - four separate read ports, read data from four independent queues - one single write port, writes to all four independent queues simultaneously - 10-bit wide read ports in single data rate, doubles internally in double data rate - 40-bit wide write port, doubles internally in double data rate - selectable single or double data rate on read and write ports - bus-matching on the write port x10/x20/x40 (sdr/ddr) (see next pages for demux and broadcast modes) functional block diagrams
2 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges list of contents: features ............................................................................................................................... ....................................................................................... 1,4 description ............................................................................................................................... ....................................................................................... 6 pin configuration ............................................................................................................................... .............................................................................. 8 pin descriptions ............................................................................................................................... ........................................................................... 9-13 device characteristics ............................................................................................................................... .................................................................... 15 dc electrical characteristics ............................................................................................................................... ........................................................... 16 ac electrical characteristics ............................................................................................................................... ............................................................ 17 ac test conditions ............................................................................................................................... ......................................................................... 18 functional description ............................................................................................................................... ............................................................... 20-29 signal descriptions ............................................................................................................................... .................................................................... 30-33 jtag timing specifications ............................................................................................................................... ........................................................ 36-40 tables: table 1 ? device configuration ................................................................................................. ................................................................................... 20 table 2 ? default programmable flag offsets ............................................................................................................................... ................................. 20 table 3 ? status flags for idt standard mode ................................................................................... .......................................................................... 23 table 4 ? status flags for fwft mode ........................................................................................... ............................................................................. 23 table 5 ? i/o voltage level associations ....................................................................................... ................................................................................ 24 table 6 ? tskew measurement .................................................................................................... .............................................................................. 34
3 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figures: figure 1. quadmux block diagram ................................................................................................ .................................................................................. 7 figure 2a. ac t est load ........................................................................................................ ........................................................................................ 18 figure 2b. lumped capacitive load, typical derating ............................................................................ ....................................................................... 18 figure 3. programmable flag offset programming methods ............................................................................................................................... ............ 21 figure 4. offset registers serial bit sequence ............................................................................................................................... ................................. 22 figure 5. bus-matching byte arrangement (mux, demux and broadcast mode) ........................................................ ............................................... 25-27 figure 6. echo read clock and data output relationship ......................................................................... ..................................................................... 35 figure 7. standard jt ag t iming ................................................................................................. .................................................................................. 36 figure 8. jtag architecture ............................................................................................................................... ............................................................ 37 figure 9. tap controller state diagram ......................................................................................... ................................................................................ 38 figure 10. master reset ........................................................................................................ ........................................................................................ 41 figure 11. partial reset for mux mode .......................................................................................... ................................................................................. 42 figure 12. partial reset for demux mode ........................................................................................ .............................................................................. 43 figure 13. partial reset for broadcast mode .................................................................................... .............................................................................. 44 figure 14. write cycle and full flag timing (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out ........................ ..................................... 45 figure 15. write cycle and full flag timing (broadcast write mode, idt standard mode, sdr to sdr) x10 in to x10 out ............ ................................ 46 figure 16. write cycle and full flag timing (demux mode, idt standard mode, sdr to sdr) x10 in to x10 out ...................... ................................... 47 figure 17. write timing (mux mode, fwft mode, sdr to sdr) x10 in to x10 out .................................................... .................................................... 48 figure 18. write timing (broadcast write mode, fwft mode, sdr to sdr) x10 in to x10 out ........................................ ............................................... 49 figure 19. write timing (demux mode, fwft mode, sdr to sdr) x10 in to x10 out .................................................. ................................................. 50 figure 20. read cycle, empty flag and first word latency (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out ........... .......................... 51 figure 21. read timing (broadcast write mode, fwft mode, sdr to sdr) x10 in to x10 out ......................................... ............................................. 52 figure 22. read timing (mux mode, fwft mode, sdr to sdr) x10 in to x10 out ..................................................... .................................................. 53 figure 23. read timing (demux mode, fwft mode, sdr to sdr) x20 in to x10 out ................................................... ............................................... 53 figure 24. read cycle, empty flag and first word latency (demux mode, idt standard mode, sdr to sdr) x20 in to x10 out ......... ........................ 54 figure 25. read cycle, empty flag and first word latency (broadcast write mode, idt standard mode, sdr to sdr) x40 in to x10 ou t .................... 55 figure 26. composite empty flag (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out .................................... ......................................... 56 figure 27. composite output ready flag (mux mode, fwft mode, sdr to sdr) x10 in to x40 out ..................................... ....................................... 56 figure 28. composite full flag (demux mode, idt standard mode, sdr to sdr) x20 in to x10 out ................................... ......................................... 57 figure 29. composite input ready flag (demux mode, fwft mode, sdr to sdr) x20 in to x10 out .................................... ...................................... 57 figure 30. echo read clock and read enable operation (mux/demux/broadcast mode, idt standard mode, ddr to ddr) x10 in to x10 ou t ........... 58 figure 31. echo rclk and echo read enable operation (mux/demux/broadcast mode, fwft mode, sdr to sdr) .......................... ........................ 59 figure 32. echo read clock and read enable operation (mux/demux/broadcast mode, idt standard mode, sdr to sdr) x10 in to x10 o ut ........... 60 figure 33. loading of programmable flag registers (idt standard and fwft modes) ................................................ ................................................ 61 figure 34. reading of programmable flag registers (idt standard and fwft modes) ................................................ ................................................ 61 figure 35. synchronous programmable almost-full flag t iming (see page for details) ............................................. ...................................................... 62 figure 36. synchronous programmable almost-empty flag t iming (see page for details) ............................................ ................................................... 62 figure 37. asynchronous programmable almost-full flag timing (see page for details) ........................................... ..................................................... 63 figure 38. asynchronous programmable almost-empty flag timing (see page for details) .......................................... .................................................. 63 figure 39. power down operation ................................................................................................ ................................................................................ 64
4 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges 8,192 x 40 16,384 x40 32,768 x 40 10 ren 0 rcs 0 rclk0 q[9:0] queue 0 oe 0 8,192 x 40 16,384 x40 32,768 x 40 10 ren 1 rcs 1 rclk1 q[19:10] queue 1 oe 1 8,192 x 40 16,384 x40 32,768 x 40 10 ren 2 rcs 2 rclk2 q[29:20] queue 2 oe 2 8,192 x 40 16,384 x40 32,768 x 40 10 ff 0 / ir 0 paf 0 ff 1 / ir 1 paf 1 ff 2 / ir 2 paf 2 ff 3 / ir 3 paf 3 ren 3 rcs 3 rclk3 q[39:30] write port flag outputs ef 0 / or 0 pae 0 ef 1 / or 1 pae 1 ef 2 / or 2 pae 2 ef 3 / or 3 pae 3 cff / cir data in x10,x20,x40 wen 0 wcs 0 wclk0 write control queue 3 is[1:0] read port flag outputs demux mode 6157 drw02 d[39:0] oe 3 queue 0 data out queue 1 data out queue 2 data out queue 3 data out 2 - fully independent status flags for every queue - composite full/input ready flag monitors currently selected queue - dedicated partial reset for every queue ? ? ? ? ? up to 200mhz operating frequency, 8gbps (sdr) and 16gbps (ddr) ? ? ? ? ? user selectable single data rate (sdr) or double data rate (ddr) modes on both the write port(s) and read port(s) ? ? ? ? ? all i/o are lvttl/ hstl/ ehstl user selectable ? ? ? ? ? 3.3v tolerant inputs in lvttl mode ? ? ? ? ? erclk and eren echo outputs on all read ports ? ? ? ? ? write chip select wcs input for each write port ? ? ? ? ? read chip select rcs input for each read port ? ? ? ? ? user selectable idt standard mode (using ef and ff flags) or fwft mode (using ir and or flags) ? ? ? ? ? composite full/ input ready flag in demux and broadcast mode ? ? ? ? ? composite empty/ output ready flag in mux mode ? ? ? ? ? independent programmable almost empty and almost full flags per queue ? ? ? ? ? dedicated serial port for flag programming ? ? ? ? ? dedicated partial reset for each individual queue ? ? ? ? ? power down pin minimizes power consumption ? ? ? ? ? 2.5v supply voltage ? ? ? ? ? available in a 324-pin plastic ball grid array (pbga) 19mm x 19mm, 1mm pitch ? ? ? ? ? ieee 1149.1 compliant jtag port provides boundary scan function, or flag programming ? ? ? ? ? low power, high performance cmos technology ? ? ? ? ? industrial temperature range (-40 c to +85 c) functional block diagrams (continued) features (continued)
5 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 8,192 x 40 16,384 x40 32,768 x 40 ff 0 / ir 0 paf 0 ff 1 / ir 1 paf 1 ff 2 / ir 2 paf 2 ff 3 / ir 3 paf 3 write port flag outputs ef 0 / or 0 pae 0 ef 1 / or 1 pae 1 ef 2 / or 2 pae 2 ef 3 / or 3 pae 3 cff / cir data in x10,x20,x40 wen 0 wcs 0 wclk0 write control queue 0 queue 1 queue 2 queue 3 read port flag outputs broadcast mode 6157 drw03 10 ren 0 rcs 0 rclk0 q[9:0] oe 0 10 ren 1 rcs 1 rclk1 q[19:10] oe 1 10 ren 2 rcs 2 rclk2 q[29:20] oe 2 10 ren3 rcs3 rclk3 q[39:30] oe3 queue 0 data out queue 1 data out queue 2 data out queue 3 data out d[39:0] functional block diagrams (continued)
6 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges description the idt72t55248/72t55258/72t55268 quadmux flow-control devices are ideal for many applications where data stream convergence and parallel buffering of multiple data paths are required. these applications may include communication and networking systems such as terabit routers, quality of service (qos) and packet prioritization routing systems, data bandwidth aggregation, data acquisition systems, wcdma baseband systems, and medical equipments. the quadmux replaces traditional methods of muxing multiple data paths at different data rates, in essence reducing external glue logic. the quadmux offers three modes of operation, mux, demux and broadcast. regardless of the mode of operation there are four internal sequential queues built using idt fifo technology and five discrete clock domains. all four queues have the same density, and the read and write ports can operate independently in single data rate (sdr) or double data rate (ddr). see figure 1, quadmux block diagram or an outline of the functional blocks within the device. the quadmux device is capable of up to 200mhz operation of all five clock inputs, all clocks being totally independent of each other. along with this high speed of operation the input and output ports are independently selectable between single data rate, sdr mode, and double data rate, ddr mode. if double data rate mode is selected data can be written into or read out of a queue on every rising and falling edge of the respective clock. for example, if the write clock is running at 200mhz and the write port(s) is/are setup for ddr mode, a data input pin has a bandwidth of 400mbps. so for a 40-bit wide bus a total bandwidth of 16gbps can be achieved. in mux mode operation a 4:1 architecture is setup, (four input ports to one output port). here there are four internal sequential queues each with a dedicated write port. data can be written into each of the dedicated write ports totally independent of any other port, each port has its own write clock input and control enables. there is a single read port that can access any one of the four queues. data is read out of a specific queue based on the address present on the output select pins. only one queue can be selected and read from at a time. all input ports are 10 bits wide and the output port has a selectable bus matching x10, x20 or x40 bus widths. a full set of flag outputs per queue are available in this mode providing the user with continuous status of each individual queue levels. in demux mode operation a 1:4 architecture is setup, (one input port to four output ports). here there is a single write port that can write data into any one of four internal queues. data is written into a specific queue based on the address present on the input select pins. only one queue can be selected and written into at a time. there are four dedicated read ports, one port for each queue. data can be read out of the four queues through the read port totally independent of any other port. each port has its own read clock input and control enables. the input port has a selectable bus matching x10, x20 or x40 bus width and all the output ports are 10-bits. a full set of flag outputs per queue are available in this mode providing the user with continuous status of each individual queue levels. in the broadcast write mode the architecture is similar to the demux mode, 1:4 (one input port to four output ports). however, there is no queue select operation in broadcast mode. instead data written into the write port is written to all four internal queues simultaneously. again there are four independent read ports, one port per queue. in broadcast mode write operations to all queues will be prevented when any one or more of the four queues are full or being partially reset. a full set of flag outputs is available in this mode providing the user with continuous status of each individual queue levels. as is typical with most idt queues, two types of data timing modes are available, idt standard mode and first word fall through (fwft) mode. this affects the device?s operation and also the flag outputs. the device provides four flag outputs, for each internal queue. the device also provides composite flags that represent the full and empty status of the currently selected queue. all read ports provide the user with a dedicated echo read enable, eren and an echo read clock, erclk output. these outputs aid in high-speed applications where synchronization of the input clock and data of a receiving device is critical. otherwise known as ?source synchronous clocking? the echo outputs provide tighter synchronization of the data transmitted from the queue to the read clock interfacing the queue outputs. a master reset input is provided and all setup and configuration pins are latched with respect to a master reset. a partial reset is provided for each internal queue. when a partial reset is performed on a queue the read and write pointers of that queue only are reset to the first memory location. the flag offset values, timing modes, and initial configurations are retained. the quadmux device has the capability of operating its i/os at either 2.5v lvttl, 1.5v hstl or 1.8v ehstl levels. a voltage reference, v ref input is provided for hstl and ehstl interfaces. the type of i/o is selected by the iosel pin. there are certain inputs that are cmos based and must be tied to either v cc or gnd. the core supply voltage of the device, v cc is always 2.5v, however the output pins have a separate supply, v ddq which can be 2.5v, 1.8v or 1.5v. the device also offers significant power savings, achieved through the use of the power down input, pd in hstl/ehstl mode. a jtag test port is provided on the quadmux device. the boundary scan is fully compliant with ieee 1149.1 standard test access port and boundary scan architecture. the jtag port can also be used to program the flag offsets.
7 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges res et logic input 6157 drw04 input mux iw[1:0] 80 80 80 80 80 ram array 0 8,192 x 40 16,384 x 40 32,768 x 40 ram array 2 8,192 x 40 16,384 x 40 32,768 x 40 ram array 1 8,192 x 40 16,384 x 40 32,768 x 40 ram array 3 8,192 x 40 16,384 x 40 32,768 x 40 output mux oe 0/1/2/3 q[39:0] (x10, x20, x40) 4 ow[1:0] rcs 0/1/2/3 jtag control (boundary scan) status flag logic read control logic write control logic read control logic write control logic status flag logic wddr wen 2 wcs 2 wclk2 rddr ren 2 rcs 2 rclk2 wddr wen 3 wcs 3 wclk3 rddr ren 3 rcs 3 rclk3 paf 2 ff 2/ ir 2 pae 2 ef 2/ or 2 paf 3 ff 3/ ir 3 pae 3 ef 3/ or 3 tck trst tms tdi tdo composite flags cef / cor cff / cir mrs prs 0/1/2/3 4 status flag logic read control logic write control logic read control logic write control logic status flag logic programmable flag control wddr wen 0 wcs 0 wclk0 rddr ren 0 rcs 0 rclk0 wddr wen 1 wcs 1 wclk1 rddr ren 1 rcs 1 rclk1 paf 0 ff 0/ ir 0 pae 0 ef 0/ or 0 paf 1 ff 1/ ir 1 pae 1 ef 1/ or 1 d[39:0] (x10, x20, x40) sclk swen sren sdo fwft/si fsel[1:0] pfm figure 1. quadmux block diagram notes: 1. this block diagram only shows the architecture for queue 0. there are a total of four queues inside this device all with the identical architecture. 2. *denotes dedicated signal for each internal queue inside the device.
8 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges a b c d e f g h j k l m n p r t wen 2 wcs 3 gnd gnd v cc v cc v cc d39 q33 q36 paf 3 os0 q35 ren 2 rcs 1 v ddq v cc v cc v cc gnd v ddq v ddq v ddq v ddq d0 d1 d6 d3 d13 wclk0 wclk1 d38 md0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd prs 0 pd v cc gnd v ddq oe 3 oe0 prs 3 vref mrs d23 oe 1 oe 2 fwft/si q9 q12 q15 12 34 56 78 910111213141516 a1 ball pad corner ow1 md1 d24 d27 d30 d33 d36 gnd v ddq wclk2 wclk3 d26 d29 d32 d35 d7 d11 d14 d16 d18 d20 d25 d22 d28 d31 d34 d37 q30 q18 eren 1 eren 2 q21 q24 q27 tdi sren sclk d12 d15 d17 d19 d21 d4 d5 fsel0 wddr d9 ow0 fsel1 v ddq iw0 gnd v cc trst iw1 tms tck gnd pfm v cc iosel v ddq gnd gnd v cc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc d2 swen q6 d10 rddr v cc prs 1 prs 2 d8 6157 drw05 u v is1 gnd gnd v cc v cc q38 rclk1 os1 rcs 2 rclk2 rclk3 ren 3 rcs 0 pae 3 rcs 3 ren 1 ren 0 17 18 erclk0 erclk1 q37 q34 q1 q0 q2 q7 q10 q13 q32 q16 q19 q20 q23 q26 q29 tdo sdo q5 eren 0 eren 3 q22 q25 q28 q31 q8 q11 q14 q17 q3 q4 erclk2 erclk3 rclk0 q39 v cc v cc v cc v ddq v cc gnd v cc v ddq v ddq v ddq gnd gnd v cc gnd gnd gnd gnd gnd v ddq gnd gnd gnd v cc gnd gnd gnd gnd gnd v ddq gnd gnd gnd gnd gnd gnd gnd v cc gnd gnd gnd gnd v ddq gnd gnd gnd v cc gnd gnd gnd v ddq gnd v cc v cc v ddq v cc v cc gnd v ddq v ddq v ddq gnd gnd v cc gnd gnd v cc gnd gnd v cc gnd gnd v cc gnd v ddq gnd gnd v ddq gnd gnd v ddq gnd gnd v ddq gnd wen 3 wen 0 wen 1 wcs 0 wcs 1 wcs 2 is0 pae 0 ef 0/ or 0 pae 1 pae 2 paf 0 cef / cor ff 0/ ir 0 paf 1 cff / cir paf 2 ff 2/ ir 2 ff 3/ ir 3 ff 1/ ir 1 ef 1/ or 1 ef 2/ or 2 ef 3/ or 3 pbga (bb324-1, order code: bb) top view pin configuration
9 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges cef / cor composite empty/ hstl-lvttl if mux mode is selected this flag will represent the exact status of the current queue being read (u6) composite output output (2) without the user having to observe the empty flag corresponding to the current queue. ready flag if demux or broadcast mode is selected this output is not used and can be left floating. cff / cir composite full/ hstl-lvttl if mux mode is selected this output is not used and can be left floating. (t6) composite input output (2) if demux mode is selected this flag will represent the exact status of the current queue being written ready flag without the user having to observe the full flag corresponding to the current queue. if broadcast mode is selected this flag goes active when any one of the four queues goes full and inactive when all four queues are not full. d[39:0] data input bus hstl-lvttl these are the data inputs for the device. data is written into the part using the respective wri te port (see pin no. input clock(s) and enable(s). if demux or broadcast mode is selected this is a single data input bus providing table for details) bus-matching of x10, x20 or x40 bits. if mux mode is selected these inputs become four separate busses to the four separate queues. d[9:0] is queue[0], d[19:10] is queue[1], d[29:20] is queue[2], d[39:30] is queue[3]. any unused inputs should be tied to gnd. note the inputs are 3.3v tolerant in lvttl mode. ef 0/1/2/3/- empty flags 0/1/2/3 hstl-lvttl this is the empty flag (standard idt mode) or output ready flag (fwft mode) corresponding or 0/1/2/3 or output ready output (2) to each of the four queues on the read port. ef indicates whether or not the queue is empty. (see pin no. flags 0/1/2/3 or indicates whether or not there is valid data available at the outputs. these flags always represent table for details) the status of the corresponding queue at all times in every mode. erclk0 echo read clock 0 hstl-lvttl if mux mode is selected this is the only echo clock output available for the read port. (r18) output (2) if demux or broadcast mode is selected this is the echo read clock output for queue 0. echo read clock always follows rclk0 with an associated delay. erclk1/2/3 echo read clock hstl-lvttl if mux mode is selected these clock outputs are inactive and can be left floating. (erclk1-t18 1/2/3 output (2) if demux or broadcast mode is selected these are the echo read clock outputs for queues 1, 2, and erclk2-u18 3 respectively. erclk3-v18) erclk1, erclk2 and erclk3 always follow rclk1, rclk2 and rclk3 respectively. eren 0 echo read enable 0 hstl-lvttl if mux mode is selected this is the echo read enable output for the read port. (j17) output (2) if demux or broadcast mode is selected this is the echo read enable input for queue 0. echo read enable is synchronous to the rclk input and is active when a read operation has occurred and a new word has been placed onto the data output bus. eren 1/2/3 echo read enable hstl-lvttl if mux mode is selected these outputs are inactive and can be left floating. ( eren 1-j16 1/2/3 output (2) if demux or broadcast mode is selected these are the echo read enable outputs for queues 1, 2 and eren 2-k16 3 respectively. eren 3-k17) echo read enable is synchronous to the rclk input and is active when a read operation has occurred and a new word has been placed onto the data output bus. ff 0/1/2/3- full flags 0/1/2/3 or hstl-lvttl this is the full flag (standard idt mode) or input ready flag (fwft mode) corresponding to ir 0/1/2/3 input ready flags output (2) each of the four queues on the write port. ff indicates whether or not the queue is full. (see pin table) 0/1/2/3 ir indicates whether or not there is valid space for writing data onto the queue. fsel [1:0] flag select hstl-lvttl during master reset, the fsel pins are used to select one of four default pae and paf offsets. (fsel1-c5 input all four internal queues are programmed to the same pae / paf offset value. values are: 00 = 7; fsel0-b6) 01 = 63; 10 = 127; 11 = 1023 fwft/si first word fall hstl-lvttl during master reset, fwft is high then the first word fall through mode is selected. if fwft (b16) through/ serial input is low the idt standard mode is selected. after master reset this pin is used for the serial data input input for the programming of the pae and paf flags offset registers. iosel i/o select cmos (1) this input determines whether the inputs will operate in lvttl or hstl/ehstl mode. if iosel (d5) input pin is high, then all inputs and outputs that are designated "lvttl or hstl" in this section will be set to lvttl format. if iosel is low then hstl/ehstl format is selected. this signal must be tied to either v cc or gnd for proper operation. is[1:0] input select hstl-lvttl if mux or broadcast mode is selected these inputs are not used and should be tied to gnd. (is1-v1 input if demux mode is selected these inputs select one of the four queues to be written into on the write is0-v2) port. the address on the input select pins is setup with respect to the rising edge of wclk0. pin descriptions symbol & name i/o type description pin no.
10 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges pin descriptions (continued) iw[1:0] input width cmos (1) in demux or broadcast, these pins are used during master reset to select the input bus size for the (iw1-c12 input device. the values are: 00 = x10; 01 = x20; 10 = x40. 11 = restricted. in mux mode these pins must iw0-c8) be tied to gnd. md[1:0] mode pin cmos (1) this mode selection pin used during master reset to select the mode of the queue. the values are: (md1-b5 input 00 = demux; 10 = mux; 01 = broadcast write; 11 = restricted. md0-b4) mrs master reset hstl-lvttl this input provides a full device reset. all set-up pins are sampled based on a master reset operation. (a5) input read and write pointers will be reset to the first location memory. all flag offsets are cleared and reset to default values determined by fsel[1:0]. oe 0 output enable 0 hstl-lvttl if mux mode is selected this is the output enable for the read port. all data output pins will be placed (a13) input into high impedance if this pin is high. if demux or broadcast mode is selected this is the output enable pin for queue 0. all data output pins of queue 0 will be placed into high impedance if this pin is high. this input is asynchronous. oe 1-(a14) output enable 1/2/3 hstl-lvttl if mux mode is selected these inputs are ignored and can be tied high. oe 2-(a15) input if demux or broadcast mode is selected these are the output enable pins queues 1, 2 and 3 oe 3-(a16) respectively. all data outputs on queue 1, queue 2 and queue 3 will be in high-impedance if the respective output enable pin is high. these inputs are asynchronous. os[1:0] output select hstl-lvttl if mux mode is selected these inputs select one of the four queues to be read from on the read port. (os1-v11 input the address on the output select pins is setup with respect to the rising edge of rclk0. os0-t12) if demux or broadcast mode is selected these inputs are not used and should be tied to gnd. ow[1:0] output width hstl-lvttl if mux mode is selected, this pin is used during master reset to select the output word width bus (ow1-b8 input size for the device. the values are: 00 = x10; 01 = x20; 10 = x40; 11 = restricted. ow0-c6) if demux or broadcast mode is selected the output word width will be x10. these pins are not used and must be tied to gnd. pae 0-(v3) programmable hstl-lvttl this is the programmable almost empty flag that can be used to pre-indicate the empty boundary pae 1-(v5) almost empty flag output (2) of each queue. the pae flags can be set to one of four default offsets determined by the state of pae 2-(v7) 0/1/2/3 fsel0 and fsel1 during master reset. the pae offset values can also be written and read from pae 3-(u10) serially by either the jtag port or the serial programming pins (sclk, fwft/si, sdo, swen , sren ). this flag can operate in synchronous or asynchronous mode depending on the state of the pfm pin during master reset. paf 0-(u4) programmable hstl-lvttl this is the programmable almost full flag that can be used to pre-indicate the full boundary of each paf 1-(t5) almost full flag output (2) queue. the paf flags can be set to one of four default offsets determined by the state of fsel0 and paf 2-(t7) 0/1/2/3 fsel1 during master reset. the paf offset values can also be written and read from serially by paf 3-(t11) either the jtag port or the serial programming pins (sclk, fwft/si, sdo, swen , sren ). this flag can operate in synchronous or asynchronous mode depending on the state of the pfm pin during master reset. pd power down hstl-lvttl this input provides considerable power saving in hstl/ehstl mode. if this pin is low, the input (b12) input level translators for all the data input pins, clocks and non-essential control pins are turned off. when pd is brought high, power-up sequence timing will have to be followed to before the inputs will be recognized. it is essential that the user respect these conditions when powering down the part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks are free running. pd does not provide any power consumption savings when the inputs are configured for lvttl pfm programmable flag cmos (1) during master reset, a high on pfm selects synchronous pae / paf flag timing, a low during (d4) mode input master reset selects asynchronous pae / paf flag timing. this pin controls all pae / paf flag outputs. prs 0-(a6) partial reset hstl-lvttl these are the partial reset inputs for each internal queue. the read, write, flag pointers, and output prs 1-(a7) 0/1/2/3 registers will all be set to zero when partial reset is activated. during partial reset, the existing mode prs 2-(a8) (idt or fwft), input/output bus width and rate mode, and the programmable flag settings are all prs 3-(a12) retained. symbol & name i/o type description pin no.
11 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges pin descriptions (continued) q[39:0] data output bus hstl-lvttl these are the data outputs for the device. data is read from the part using the respective read see pin no. output (2) port clock(s) and enable(s). if mux mode is selected this is a single data output bus providing bus- table for details) matching of x10, x20 or x40 bits. if demux or broadcast mode is selected these outputs become four separate busses from the four separate queues. q[9:0] is queue[0], q[19:10] is queue[1], q[29:20] is queue[2], q[39:30] is queue[3]. any unused outputs should be left floating. note, that the outputs are not 3.3v tolerant. rclk0 read clock 0 hstl-lvttl if mux mode is selected this is the clock input for the read port. all read port operations will be (v17) input synchronous to this clock input. if demux or broadcast mode is selected this is the read clock input for queue 0. all read port operations on queue 0 will be synchronous to this clock input. rclk1-(v16) read clock 1/2/3 hstl-lvttl if mux mode is selected these clock inputs are ignored and if unused can be tied to gnd. rclk2-(v15) input if demux or broadcast mode is selected these are the read clock inputs for queues 1, 2, and 3 rclk3-(v14) respectively. all read port operations on queue 1, queue 2 and queue 3 will be synchronous to clock inputs rclk1, rclk2 and rclk3 respectively. rcs 0 read chip select 0 hstl-lvttl if mux mode is selected this is the read chip select input for the read port. all read operations will occur (u13) input synchronous to the rclk0 input provided that ren 0 and rcs 0 are low. if demux or broadcast mode is selected this is the read chip select input for queue 0. all read operations on queue 0 will occur synchronous to the rclk0 input provided that ren 0 and rcs 0 are low. rcs 1-(t13) read chip select hstl-lvttl if mux mode is selected these inputs are ignored and can be tied high. rcs 2-(v12) 1/2/3 input if demux or broadcast mode is selected these are the read chip select inputs for queues 1, 2 and rcs 3-(u12) 3 respectively. all read operations on queue 1, queue 2 and queue 3 will occur synchronous to the rclk1, 2 and 3 input respectively, provided that the corresponding read enable and read chip select inputs are low. rddr read port ddr cmos (1) during master reset, this pin selects the output port to operate in ddr or sdr format. if rddr is high, (b7) input then a word is read on the rising and falling edge of the appropriate rclk0, 1, 2 and 3 input. if rddr is low, then a word is read only on the rising edge of the appropriate rclk0, 1, 2 and 3 inputs. ren 0 read enable 0 hstl-lvttl if mux mode is selected this is the read enable input for the read port. all read operations will occur (u15) input synchronous to the rclk0 clock input provided that ren 0 and rcs 0 are low. if demux or broadcast mode is selected this is the read enable input for queue 0. all read operations on queue 0 will occur synchronous to the rclk0 input provided that ren 0 and rcs 0 are low. ren 1-(u14) read enable 1/2/3 hstl-lvttl if mux mode is selected these inputs are ignored and can be tied high. ren 2-(t14) input if demux or broadcast mode is selected these are the read enable inputs for queues 1, 2 and 3 ren 3-(v13) respectively. all read operations on queue 1, queue 2 and queue 3 will occur synchronous to the rclk0, 1, 2 and 3 inputs respectively, provided that the corresponding read enable and read chip select inputs are low. sclk serial clock hstl-lvttl serial clock for writing and reading the pae and paf offset registers. on the rising edge of each (b14) input sclk, when swen is low, one bit of data is shifted from the fwft/si pin into the pae and paf offset registers. on the rising edge of each sclk, when sren is low, one bit of data is shifted out of the pae and paf offset registers. the reading of the pae and paf offset registers are non-destructive. if programming of the pae / paf offset registers is done via the jtag port, this input must be tied to v cc . sdo serial data output lvttl this output is used to read data from the programmable flag offset registers. it is used in conjunction (c17) output (2) with the sren and sclk signals. sren serial read enable hstl-lvttl when sren is brought low before the rising edge of sclk, the contents of the pae and paf (b15) input offset registers are copied to a serial shift register. while sren is maintained low, on each rising edge of sclk, one bit of data is shifted out of this serial shift register through the sdo output pin. if programming of the pae / paf offset registers is done via the jtag port, this input must be tied to v cc . swen serial write enable hstl-lvttl on each rising edge of sclk when swen is low, data from the fwft/si pin is serially loaded (c16) input into the pae and paf registers. if programming of the pae / paf offset registers is done via the jtag port, this input must be tied to v cc . on each clock, data is shifted into and through the actual pae and paf registers, so the value of the registers is changed on each clock symbol & name i/o type description pin no.
12 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges tck (3) jtag clock hstl-lvttl clock input for jtag function. one of four terminals required by ieee standard 1149.1-1990. test (c13) input operations of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and output tdo change on the falling edge of tck. if the jtag function is not used this signal needs to be tied to gnd. tdi (3) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan (b13) input input operation, test data is serially loaded via the tdi on the rising edge of tck to either the instruction register, id register, bypass register or boundary scan chain. an internal pull-up resistor forces tdi high if left unconnected. tdo (3) jtag test data hstl-lvttl one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan (b17) output output operation, test data is scanned to the tdo output on the falling edge of tck from either the instruction register, id register, bypass register and boundary scan chain. this output is high impedance except when shifting, while in shift-dr and shift-ir controller states. tms (3) jtag mode select hstl-lvttl tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms directs (c14) input the device through its tap controller states sampled on the rising edge of tck. an internal pull-up resistor forces tms high if left unconnected. trst (3) jtag reset hstl-lvttl trst is an asynchronous reset pin for the jtag controller. the jtag tap controller is automatically (c15) input reset upon power-up. if the tap controller is not properly reset then the queue outputs will always be in high-impedance. if the jtag function is used but the user does not want to use trst , then trst can be tied with mrs to ensure proper queue operation. if the jtag function is not used then this signal needs to be tied to gnd. an internal pull-up resistor forces trst high if left unconnected. wclk0 write clock 0 hstl-lvttl if mux mode is selected this is the clock input for queue 0. all write port operations to queue 0 will (f1) input be synchronous to this clock input. if demux or broadcast mode is selected this is the clock input for the write port. all write port operations will be synchronous to this clock input. sampled on the rising edge of wclk and independent of wddr. wclk1-(g1) write clock 1/2/3 hstl-lvttl if mux mode is selected these are the clock inputs for queues 1, 2, and 3 respectively. all write wclk2-(h1) input port operations on queue1, queue 2 and queue 3 will be synchronous to clock inputs wclk1, wclk3-(j1) wclk2 and wclk3 respectively. if demux or broadcast mode is selected these clock inputs are ignored and can be tied to gnd. wcs 0 write chip select 0 hstl-lvttl if mux mode is selected this is the write chip select input for queue 0. all write operations on queue 0 (u1) input will occur synchronous to the wclk0 input provided that wen 0 and wcs 0 are low. if demux or broadcast mode is selected this is the write chip select input for the write port. all write operations will occur synchronous to the wclk0 input provided that wen 0 and wcs 0 are low. sampled on the rising edge of wclk and independent of wddr. wcs 1-(u2) write chip select hstl-lvttl if mux mode is selected these are the write chip select inputs for queues 1, 2 and 3 respectively. all wcs 2-(u3) 1, 2, 3 input write operations on queue 1, queue 2 and queue 3 will occur synchronous to the wclk1, 2 and 3 wcs 3-(t1) respectively, provided that the corresponding write enable and write chip select inputs are low. sampled on the rising edge of wclk and independent of wddr. if demux or broadcast mode is selected these inputs are ignored and can be tied high. wddr write port ddr cmos (1) during master reset, this pin selects the input port to operate in ddr or sdr format. if wddr is high, (c7) input then a word is written on the rising and falling edge of the appropriate wclk0, 1, 2 and 3 input. if wddr is low, then a word is written only on the rising edge of the appropriate wclk1, 1, 2 and 3 inputs. wen 0 write enable 0 hstl-lvttl if mux mode is selected this is the write enable input for queue 0. all write operations on queue 0 will (t2) input occur synchronous to the wclk0 input provided that wen 0 and wcs 0 are low. if demux or broadcast mode is selected this is the write enable input for the write port. all write operations will occur synchronous to the wclk0 clock input provided that wen 0 and wcs 0 are low. wen 1-(t3) write enable 1/2/3 lvttl if mux mode is selected these are the write enable inputs for queues 1, 2 and 3 respectively. all write wen 2-(r1) operations on queue 1, queue 2 and queue 3 will occur synchronous to the wclk1, 2 and 3 inputs wen 3-(r2) respectively, provided that the corresponding write enable and write chip select inputs are low. if demux or broadcast mode is selected these inputs are ignored and can be tied high. pin descriptions (continued) symbol & name i/o type description pin no.
13 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges pin descriptions (continued) symbol & name i/o type description pin no. v cc +2.5v supply power these are v cc core power supply pins and must all be connected to a +2.5v supply rail. (see pin table) v ddq output rail voltage power this pin should be tied to the desired voltage rail for providing to the output drivers. nominally 1.5v (see pin table) or 1.8v for hstl, 2.5v for lvttl. gnd ground pin ground these ground pins are for the core device and must be connected to the gnd rail. (see pin table) vref reference voltage analog this is a voltage reference input and must be connected to a voltage level determined in the voltage (a4) recommended dc operating conditions section. this provides the reference voltage when using hstl class inputs. if hstl class inputs are not being used, this pin must be connected to gnd. pin number table symbol name i/o type pin number d[39:0] data input bus hstl-lvttl d39-r3, d(38-36)-p(1-3), d(35-33)-n(1-3), d(32-30)-m(1-3), d(29-27)-l(1-3), d(26-24)-k(1-3), input d(23,22)-j(3,2), d(21,20)-h(3,2), d(19,18)-g(3,2), d(17,16)-f(3,2), d(15-13)-e(3-1), d(12-10)-d(3-1), d(9-6)-c(4-1), d(5-3)-b(3-1), d(2-0)-a(3-1) ef0/1/2/3- empty flags0-3 or hstl-lvttl ef 0/ or 0-v4, ef 1/ or 1-u5, ef 2/ or 2-u7, ef 3/ or 3-v10 or0/1/2/3 output ready flags 0-3 output (2) ff0/1/2/3- full flags0-3 or hstl-lvttl ff 0/ ir 0-t4, ff 1/ ir 1-v6, ff 2/ ir 2-t10, ff 3/ ir 3-u11 ir0/1/2/3 input ready flags 0-3 output (2) q[39:0] data out put bus hstl-lvttl q(39,38)-u(17,16), q(37-35)-t(17-15), q(34,33)-r(17,16), q(32-30)-p(18-16), q(29-27)-n(18-16), output (2) q(26-24)-m(18-16), q(23-21)-l(18-16), q20-k18, q19-j18, q(18-16)-h(16-18), q(15-13)-g(16-18), q(12-10)-f(16-18), q(9-7)-e(16-18), q(6-4)-d(16-18), q3-c18, q2-b18, q(1-0)-a(18-17) v cc +2.5v supply power a9, b9, c9, d(6,9), e(4-9), f(4,5), g(4,5), h(4,5), j(4,5), k(4,5), l(4,5), m(4,5), n(4,5), p(4-8), r(4-8), t8, u8, v8 v ddq o/p rail voltage power a11, b11, c11, d(11-15), e(11-15), f(14,15), g(14,15), h(14,15), j(14,15), k(14,15), l(14,15), m(14,15), n(14,15), p(11-15), r(11-15) gnd ground pin ground a10, b10, c10, d(7,8,10), e10, f(6-13), g(6-13), h(6-13), j(6-13), k(6-13), l(6-13), m(6-13), n(6-13), p(9,10), r(9,10), t9, u9, v9 notes: 1. all cmos pins should remain unchanged. cmos format means that the pin is intended to be tied directly to v cc or gnd and these particular pins are not tested for v ih or v il . 2. all unused outputs may be left floating. 3. these pins are for the jtag port. please refer to pages 36-40, figure 7-9 for jtag information.
14 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges set-up, configuration & reset pins regardless of the mode of operation, (mux, demux or broadcast), the following inputs must always be used. these inputs must be set-up with respect to master reset as they are latched during master reset. wddr ? write port ddr/sdr selection rddr ? read port ddr/sdr selection md[1:0] ? mode selection ow[1:0] ? output width iw[1:0] ? input width fsel[1:0] ? flag offset default values iosel ? i/o level selection pfm ? programmable flag mode fwft/si ? first word fall through or standard idt mode flag timing selection mux mode the following inputs/ outputs should be used when mux mode is selected by the user: inputs: wclk0, wclk1, wclk2, wclk3 ? four write port clocks wen 0, wen 1, wen 2, wen 3 ? four write port enables wcs 0, wcs 1, wcs 2, wcs 3 ? four write port chip selects os[1:0] - output select rclk0 ? read port clock ren 0 ? read port enable rcs 0 ? read port chip select oe 0 ? read port output enable outputs: erclk0 ? read port echo read clock eren 0 ? read port echo read enable ef 0/ or 0, ef 1/ or 1, ef 2/ or 2, ef 3/ or 3 ? four read port empty/output ready flags pae 0, pae 1, pae 2, pae 3 ? four read port programmable almost empty flags paf 0, paf 1, paf 2, paf 3 ? four write port programmable almost full flags ff 0/ ir 0, ff 1/ ir 1, ff 2/ ir 2, ff 3/ ir 3 ? four write port full/ input ready flags cef / cor ? composite empty/output ready flag on read port serial port the following pins are used for writing and reading the programmable flag offsets values: sclk ? serial clock swen ? serial write enable sren ? serial read enable fwft/si ? serial data in sdo ? serial data out demux or broadcast mode the following inputs/outputs should be used when demux or broadcast write mode is selected by the user: inputs: is[1:0] - input select, demux mode only, not used in broadcast mode. wclk0 ? write port clock wen 0 ? write port enable wcs 0 ? write port chip select rclk0, rclk1, rclk2, rclk3 ? four read port clocks ren 0, ren 1, ren 2, ren 3 ? four read port enables rcs 0, rcs 1, rcs 2, rcs 3 ? four read port chip selects oe 0, oe 1, oe 2, oe 3 ? four read port output enables outputs: erclk0, erclk1, erclk2, erclk3 ? four read port echo read clock outputs eren 0, eren 1, eren 2, eren 3 ? four read port echo read enable outputs ef 0/ or 0, ef 1/ or 1, ef 2/ or 2, ef 3/ or 3 ? four read port empty/output ready flags ff 0/ ir 0, ff 1/ ir 1, ff 2/ ir 2, ff 3/ ir 3 ? four write port full/input ready flags paf 0, paf 1, paf 2, paf 3 ? four write port programmable almost full flags pae 0, pae 1, pae 2, pae 3 ? four read port programmable almost empty flags cff / cir ? composite full/ input ready flag on write port quadmux i/o usage summary
15 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. compliant with jedec jesd8-5. v cc terminal only. symbol parameter (1) conditions max. unit c in (2,3) input v in = 0v 10 (3) pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. 3. c in for vref is 20pf. symbol parameter min. typ. max. unit v cc supply voltage 2.375 2.5 2.625 v v ddq output supply voltage ? lvttl 2.375 2.5 2.625 v ? ehstl 1.7 1.8 1.9 v ? hstl (2) 1.4 1.5 1.6 v v ref voltage reference input ? ehstl 0.8 0.9 1.0 v ? hstl (2) 0.68 0.75 0.9 v gnd supply voltage 0 0 0 v v ih input high voltage ? lvttl 1.7 ? 3.45 v ? ehstl v ref +0.1 ? v ddq +0.3 v ? hstl (2) v ref +0.1 ? v ddq +0.3 v v il input low voltage ? lvttl ? ? 0.7 v ? ehstl v ref -0.3 ? v ref -0.1 v ? hstl (2) v ref -0.3 ? v ref -0.1 v t a operating temperature commercial 0 ? +70 c t a operating temperature industrial -40 ? +85 c recommended dc operating conditions notes: 1. v ref is only required for hstl or ehstl inputs. v ref should be tied low for lvttl operation. 2. compliant with jedec jesd8-6. absolute maximum ratings symbol rating com'l & ind'l unit v term terminal voltage ?0.5 to +3.6 (2) v with respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?? to +? ma
16 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges dc electrical characteristics (industrial: v cc = 2.5v 0.125v, t a = -40 c to +85 c) symbol parameter min. max. unit i li input leakage current ?10 +10 a i lo output leakage current ?10 +10 a v oh (7) output logic ?1? voltage, i oh = ?8 ma @lvttl v ddq -0.4 ? v i oh = ?8 ma @ehstl v ddq -0.4 ? v i oh = ?8 ma @hstl v ddq -0.4 ? v v ol output logic ?0? voltage, i ol = 8 ma @lvttl ? 0.4 v i ol = 8 ma @ehstl ? 0.4 v i ol = 8 ma @hstl ? 0.4 v i cc1 (1,2,3) active v cc current -- lvttl ? 239 ma (see note 8 and 9 for test conditions) -- ehstl ? 336 ma -- hstl ? 332 ma i cc3 (1,2,3) standby v cc current (mux mode) -- lvttl ? 112 ma (see note 10 and 11 for test conditions) -- ehstl ? 188 ma -- hstl ? 186 ma i cc5 (1,2,3) power down v cc current (mux mode) -- lvttl ? 9 ma (see note 12 and 13 for test conditions) -- ehstl ? 26 ma -- hstl ? 24 ma notes: 1. both wclk and rclk toggling at 20mhz. 2. data inputs toggling at 10mhz. 3. typical i cc1 calculation : for lvttl i/o i cc1 (ma) = 10 x f s , f s = wclk frequency = rclk frequency (in mhz) for hstl or ehstl i/o i cc1 (ma) = 72+ (10 x f s ), f s = wclk frequency = rclk frequency (in mhz) 4. typical i ddq calculation: with data outputs in high-impedance: i ddq (ma) = 0.78 x f s with data outputs in low-impedance: i ddq (ma) = c l x v ddq x f s x n /2000 fs = wclk frequency = rclk frequency (in mhz), v ddq = 2.5v for lvttl; 1.5v for hstl; 1.8v for ehstl t a = 25c, c l = capacitive load (pf), n = number of bits switching 5. total power consumed: pt = [(v cc x i cc ) + (v ddq x i ddq )]. i oh = -8ma for all voltage levels. 6. i oh 8ma, i ol -8ma. 7. outputs are not 3.3v tolerant. 8. v cc = 2.5v, wclk0-3 = rclk0 = 20mhz, wen 0-3 = ren 0 = low, wcs 0-3 = rcs 0 = low, oe = low, pd = high. 9. v cc = 2.5v, wclk0 = rclk0-3 = 20mhz, wen 0 = ren 0-3 = low, wcs 0 = rcs 0-3 = low, oe 0-3 = low, pd = high. 10. v cc = 2.5v, wclk0-3 = rclk0 = 20mhz, wen 0-3 = ren 0 = high, wcs 0-3 = rcs 0 = high, oe = low, pd = high. 11. v cc = 2.5v, wclk0 = rclk0-3 = 20mhz, wen 0 = ren 0-3 = high, wcs 0 = rcs 0-3 = high, oe 0-3 = low, pd = high. 12. v cc = 2.5v, wclk0-3 = rclk0 = 20mhz, wen 0-3 = ren 0 = high, wcs 0-3 = rcs 0 = high, oe = low, pd = low. 13. v cc = 2.5v, wclk0 = rclk0-3 = 20mhz, wen 0 = ren 0-3 = high, wcs 0 = rcs 0-3 = high, oe 0-3 = low, pd = low.
17 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges ac electrical characteristics (commercial: v cc = 2.5v 0.15v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.15v, t a = -40 c to +85 c; jedec jesd8-a compliant) commercial & industrial commercial & industrial idt72t55248l5 idt72t55248l6-7 idt72t55258l5 idt72t55258l6-7 idt72t55268l5 idt72t55268l6-7 symbol parameter min. max. min. max. unit f s clock cycle frequency (wclk & rclk) ? 200 ? 150 mhz t a data access time 0.6 3.6 0.6 3.8 ns t clk clock cycle time 5 ? 6.7 ? ns t clkh clock high time 2.3 ? 2.8 ? ns t clkl clock low time 2.3 ? 2.8 ? ns t ds data setup time 1.5 ? 2.0 ? ns t dh data hold time 0.5 ? 0.5 ? ns t ens enable setup time 1.5 ? 2.0 ? ns t enh enable hold time 0.5 ? 0.5 ? ns f c clock cycle frequency (sclk) ? 10 ? 10 mhz t aso serial output data access time ? 20 ? 20 ns t sclk serial clock cycle 100 ? 100 ? ns t sckh serial clock high 45 ? 45 ? ns t sckl serial clock low 45 ? 45 ? ns t sds serial data in setup 15 ? 15 ? ns t sdh serial data in hold 5 ? 5 ? ns t sens serial enable setup 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? ns t rs reset pulse width 200 ? 200 ? ns t rss reset setup time 15 ? 15 ? ns t rsr reset recovery time 10 ? 10 ? ns t rsf reset to flag and output time ? 12 ? 15 ns t olz ( oe - q n) (2) output enable to output in low-impedance 0.6 3.6 0.8 3.8 ns t ohz (2) output enable to output in high-impedance 0.6 3.6 0.8 3.8 ns t oe output enable to data output valid 0.6 3.6 0.8 3.8 ns t wff write clock to ff or ir ? 3.6 ? 3.8 ns t ref read clock to ef or or ? 3.6 ? 3.8 ns t cef read clock to composite ef or or ? 3.6 ? 3.8 ns t cff write clock to composite ff or ir ? 3.6 ? 3.8 ns t pafs write clock to synchronous programmable almost-full flag ? 3.6 ? 3.8 ns t paes read clock to synchronous programmable almost-empty flag ? 3.6 ? 3.8 ns t pafa write clock to asynchronous programmable almost-full flag ? 10 ? 12 ns t paea read clock to asynchronous programmable almost-empty flag ? 10 ? 12 ns t erclk rclk to echo rclk output ? 4.0 ? 4.3 ns t clken rclk to echo ren output ? 3.6 ? 3.8 ns t d time between data switching and erclk edge 0.4 ? 0.5 ? ns t rcslz rclk to active from high-impedance ? 3.6 ? 3.8 ns t rcshz rclk to high-impedance ? 3.6 ? 3.8 ns t skew1 (3) skew time between rclk and wclk for ef / or and ff / ir 4? 5?ns t skew2 skew time between rclk and wclk for ef / or and ff / ir in5? 7?ns ddr mode t skew3 skew time between rclk and wclk for pae and paf 5? 7?ns notes: 1. values guaranteed by design, not currently tested. 2. this applies to both ddr and sdr modes of operation.
18 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges ac test loads figure 2a. ac test load 6157 drw06 50 ? v ddq /2 i/o z 0 = 50 ? input pulse levels 0.25 to 1.25v input rise/fall times 0.4ns input timing reference levels 0.75 output reference levels v ddq /2 hstl 1.5v ac test conditions input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels v cc /2 output reference levels v ddq /2 lvttl 2.5v ac test conditions note: 1. v ddq = 1.5v. note: 1. for lvttl, v cc = v ddq = 2.5v. input pulse levels 0.4 to 1.4v input rise/fall times 0.4ns input timing reference levels 0.9 output reference levels v ddq /2 extended hstl 1.8v ac test conditions note: 1. v ddq = 1.8v. figure 2b. lumped capacitive load, typical derating 6157 drw06a 6 5 4 3 2 1 20 30 50 80 100 200 capacitance (pf) ? t cd (typical, ns)
19 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges output enable & disable timing v ih oe v il t oe & t olz 100mv 100mv t ohz 100mv 100mv single output normally low single output normally high v ol v oh v ddq /2 6157 drw07 output enable output disable v ddq /2 v ddq /2 v ddq /2 t olz current data in output register t oe v ddq /2 output bus v ddq /2 t ohz read chip select enable & disable timing notes: 1. ren is high. 2. oe is low. v ih rcs v il t ens t enh t rcslz rclk v ddq 2 v ddq 2 100mv 100mv t rcshz 100mv 100mv output normally low output normally high v ol v oh v ddq 2 v ddq 2 6157 drw08 notes: 1. ren is high. 2. rcs is low.
20 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges functional description master reset & device configuration - mrs during master reset the device operation is determined, this includes the following: 1. mux, demux or broadcast mode 2. idt standard or first word fall through (fwft) flag timing mode 3. single or double data rates on both the write and read ports 4. programmable flag mode, synchronous or asynchronous timing 5. write and read port bus widths, x10, x20 or x40 6. default offsets for the programmable flags, 7, 63, 127 or 1023 7. lvttl or hstl i/o level selection 8. input and output queue selection the state of the configuration inputs during a master reset will determine which of the above modes are selected. a master reset comprises of pulsing the mrs input ping from high to low for a period of time (t rs ) with the configuration inputs held in their respective states. table 1 summarizes the configuration modes available doing master reset. the are described as follows: mux/demux/broadcast. this mode is selected using the md[1:0] inputs. if during master reset, md1 is high and md0 is low then mux mode is selected. if md1 and md2 are low then demux is selected. if md1 is low and md0 is high then broadcast mode is selected. idt standard or fwft mode . the two available flag timing modes are selected using the fwft/si input. if fwft/si is low during master reset then idt standard mode is selected, if it is high then fwft mode is selected. single data rate (sdr) or double data rate (ddr). the input/output data rates are port selectable. this is a versatile feature that allows the user to select either sdr or ddr on the write port(s) and/or read(s) port using the wddr and/or rddr inputs. if wddr is low during master reset then the write port(s) will function in sdr mode, if it is high then the write port will be ddr mode. if rddr is low during master reset then the read port(s) will function in sdr mode, if it is high then the read port will be ddr mode. note that wddr will select the data rate mode for the single write port in demux and broadcast mode and all four write ports in mux mode. likewise, rddr will select the data rate mode for the single read port in mux mode and all four read ports in demux and broadcast mode. programmable almost empty/full flags . these flags can operate in either synchronous or asynchronous timing mode. if the programmable flag input, pfm is high during master reset then all programmable flags will operate in a synchronous manner, meaning the pae flags are double buffered and updated based on the rising edge of its respective read clocks. the paf flags are also double buffered and updated based on the rising edge of its respective write clocks. if it is low then all programmable flags will operate in an asynchronous manner, meaning the pae and paf flags are not double buffered and will update through the internal counter after a nominal delay. selectable bus width . the bus width can be selected on the write port in demux and broadcast mode and on the read port in mux mode. in demux and broadcast mode the write port width is selected using the iw[1:0] inputs. if iw0 and iw1 are low then the write port will be 10 bits wide, if iw0 is low and iw1 is high then the write port will be 20 bits wide, if iw0 is high and iw1 is low then the write port will be 40 bits wide. note, in demux and broadcast mode all read ports are 10 bits wide. in mux mode the read port width is selected using the ow[1:0] inputs. if ow0 and 0w1 are low then the read port will be 10 bits wide, if ow0 is low and ow1 are high then the read port will be 20 bits wide, if ow0 is high and ow1 are low then the read port will be 40 bits wide. note, in mux mode all write ports are 10 bits wide. programmable flag offset values. these offset values can be user programmed or they can be set to one of four default values during a master reset. for default programming, the state of the fsel[1:0] inputs during master table 1 device configuration pins values configuration md[1:0] 00 demux 10 mux 01 broadcast write 11 restricted fwft/si 0 idt standard 1 fwft wddr 0 single data rate write port 1 double data rate write port rddr 0 single data rate read port 1 double data rate read port pfm 0 asynchronous operation of pae and paf outputs 1 synchronous operation of pae and paf outputs iw[1:0] 00 write port is 10 bits wide 01 write port is 20 bits wide 10 write port is 40 bits wide 11 restricted ow[1:0] 00 read port is 10 bits wide 01 read port is 20 bits wide 10 read port is 40 bits wide 11 restricted fsel[1:0] 00 programmable flag offset registers value = 7 01 programmable flag offset registers value = 63 10 programmable flag offset registers value = 127 11 programmable flag offset registers value = 1023 iosel 0 all applicable i/os (except cmos) are lvttl 1 all applicable i/os (except cmos) are hstl/ehstl is[1:0] mux/broadcast mode demux mode 00 not used queue0 01 not used queue1 10 not used queue2 11 not used queue3 os[1:0] mux mode demux/broadcast mode 00 queue0 not used 01 queue1 not used 10 queue2 not used 11 queue3 not used idt72t55248 idt72t55258 idt72t55268 fsel1 fsel0 offsets n,m 00 7 0163 1 0 127 1 1 1,023 table 2 default programmable flag offsets notes: 1. in default programming, the offset value selected applies to all internal queues. 2. to program different offset values for each queue, serial programming must be used.
21 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges reset will determine the value. table 1 lists the four offset values and how to select them. for programming the offset values to a specific number, use the serial programming signals (sclk, swen , sren , fwft/si) to load the value into the offset register. you may also use the jtag port on this device to load the offset value. keep in mind that you must disable the serial programming signals if you plan to use the jtag port for loading the offset values. to disable the serial programming signals, tie sclk, swen , sren , and si to v cc . a thorough explanation of the serial and jtag programming of the flag offset values is provided in the next section. i/o level selection. the i/os can be selected for either 2.5v lvttl levels or 1.5v hstl / 1.8v ehstl levels. the state of the iosel input will determine which i/o level will be selected. if iosel is high then the applicable i/os will be 1.5v hstl or 1.8v ehstl, depending on the voltage level applied to v ddq and v ref . for hstl, v ddq and v ref = 0.75v and for ehstl v ddq and v ref = 0.9v. if iosel is low then the applicable i/os will be 2.5v lvttlv ref = 0. as noted in the pin description section, iosel is a cmos input and must be tied to either v cc or gnd for proper operation. input and output selection. during master reset, the value of is[1:0] and os[1:0] will be held constant and indicates which internal queue the read and write port will select for initial operation. data will be written to or read from this internal queue on the first valid write and read operation after master reset. serial writing and reading of offset registers these offset registers can be loaded with a default value or they can be user programmed with another value. one of four default values are detected based on the state of the fsel[1:0] inputs, discussed in the functional description section earlier. user programming of the offset values can be performed by sclk tdi* 0008 tck* swen 0 sren 1 no operation iw/ow = x40 serial read from registers: 104 bits for the idt72t55248 112 bits for the idt72t55258 120 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) idt72t55258 idt72t55268 idt72t55278 serial write into register: 104 bits for the idt72t55248 112 bits for the idt72t55258 120 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) 6157 drwaa iw/ow = x20 serial write into register: 112 bits for the idt72t55248 120 bits for the idt72t55258 128 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) 0007 11 serial read from registers: 112 bits for the idt72t55248 120 bits for the idt72t55258 128 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) no operation don?t care except 0008 & 0007 10 xx iw/ow = x10 serial write into register: 120 bits for the idt72t55248 128 bits for the idt72t55258 136 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) serial read from registers: 120 bits for the idt72t55248 128 bits for the idt72t55258 136 bits for the idt72t55268 1 bit for each rising sclk edge starting with empty offset (lsb) ending with full offset (msb) no operation notes: * programming done using the jtag port. 1. the programming methods apply to both idt standard mode and fwft mode. 2. parallel programming is not featured in this device. 3. the number of bits includes programming to all four dedicated pae / paf offset registers. figure 3. programmable flag offset programming methods either the dedicated serial programming port or the jtag port. the dedicated serial port can be used to load or read the contents of the offset registers. the offset registers are programmed and read sequentially and behave similar to a shift register. the serial read and write operations are performed by the dedicated sclk, fwft/si, swen , sren , and sdo pins. the total number of bits per device is listed in figure? programmable flag offset programming sequence . these bits account for all four pae / paf offset registers in the device. to write to the offset registers, set the serial write enable signal active (low), and on each rising edge of sclk one bit from the fwft/si pin is serially shifted into the flag offset register chain. once the complete number of bits has been programmed into all four registers, the programming sequence is complete. the programming sequence is listed in figure ? to read values from the offsets registers, set the serial read enable active (low). then on each rising edge of sclk, one bit is shifted out to the serial data output. the serial read enable must be kept low throughout the entire read operation. to stop reading the offset register, disable the serial read enable (high). there is serial read enable to sclk time for reading the offset registers, as the offset register data for each queue is temporarily stored in a scan chain. when data has been completely read out of the offset registers, any additional read operations to the offset register will result in zeros as the output data. reading and writing of the offset registers can also be accomplished using the jtag port. to write to the offset registers using jtag, set the instructional register to the offset write command (hex value = 0x0008). the jtag port will load data into each of the offset registers in a similar fashion as the serial programming described above. to read the values from the offset registers, set the instructional register to the offset read command (hex value = 0x0007). the
22 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges tdo of the jtag port will output data in a similar fashion as the serial programming described above. the number of bits required to load the offset registers is dependent on the size of the device selected. each offset register requires different total number of bits depending on input and output bus width configuration. this total must be programmed into the device in order for all the flags to be programmed correctly. to change values of one or more offset register, all of the registers must be reprogrammed serially again. see figure? offset registers serial bit se- quence . timing modes: idt standard vs first word fall through (fwft) mode the idt72t55248/72t55258/72t55268 support two different timing modes of operation: idt standard mode or first word fall through (fwft) mode. the selection of which mode will operate is determined during master reset, by the state of the fwft input. during master reset, if the fwft pin is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the queue. it also uses the full flag ( ff ) to indicate whether or not the queue has any free space for writing. in idt standard mode, every word read from the queue, including the first, must be requested using the read enable ( ren ) and rclk. if the fwft pin is high during master reset, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs. it also uses input ready ( ir ) to indicate whether or not the queue has any free space for writing. in the fwft mode, the first word written to an empty queue goes directly to output bus after three rclk rising edges, applying rcs = low is not necessary. however, subsequent words must be accessed using the ( rcs ) and rclk. various signals, in both inputs and outputs operate differently depending on which timing mode is in effect. the timing mode selected affects all internal queues equally. idt standard mode in this mode, the status flags ff , paf , pae , and ef operate in the manner outlined in table 3. to write data into the queue, write enable ( wen ) and wcs must be low. data presented to the data in lines will be clocked into the queue on subsequent transitions of the write clock (wclk). after the first write is performed, the empty flag ( ef ) will go high after three clock latency. subsequent writes will continue to fill up the queue. the programmable almost- empty flag ( pae ) will go high after n + 1 words have been loaded into the queue, where n is the empty offset value. the default setting for these values are listed in table ?. this parameter is also user programmable as described in the serial writing and reading of offset registers section. continuing to write data into the queue without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (8,192-m) writes for the idt72t55248, (16,384-m) writes for the idt72t55258, and (32,768-m) writes for the idt72t55268. this is assuming the i/o bus width is configured to x40. if the i/o is x20, then paf will go low after (16,384-m) writes for the idt72t55248, (32,768-m) writes for the idt72t55258, and (65,536-m) writes for the idt72t55268. if the i/o is x10, then paf will go low after (32,768-m) writes for the idt72t55248, (65,536-m) writes for the idt72t55258, and (131,072-m) writes for the idt72t55268. the offset ?m? is the full offset value. the default setting for these values are listed in table 3. this parameter is also user programmable. see the section on serial writing and reading of offset registers for details. when the queue is full, the full flag ( ff ) will go low, inhibiting further write operations. if no reads are performed after a reset, ff will go low after d writes to the queue. if the i/o bus width is configured to x40, then d = 8,192 writes for the idt72t55248, 16,384 writes for the idt72t55258, and 32,768 writes for the idt72t55268. if the i/o is x20, then d = 16,384 writes for the idt72t55248, 32,768 writes for the idt72t55258, and 65,536 writes for the idt72t55268. if the i/o is x10, then d = 32,768 writes for the idt72t55248, 65,536 writes for the idt72t55258, and 131,072 writes for the idt72t55268. 6157 drwab offset register pae 3 paf 3 pae 2 paf 2 pae 1 paf 1 pae 0 paf 0 14 - 26 27 - 39 40 - 52 53 - 65 66 - 78 1 - 13 79 - 91 92 - 104 serial bits idt72t55248 iw/ow = x20 or idt72t55258 iw/ow = x40 idt72t55248 iw/ow = x20 or idt72t55258 iw/ow = x20 or idt72t55268 iw/ow = x40 idt72t55248 iw/ow = x40 idt72t55268 iw/ow = x10 idt72t55258 iw/ow = x10 or idt72t55268 iw/ow = x20 15 - 28 29 - 42 43 - 56 57 - 70 71 - 84 1 - 14 85 - 98 99 - 112 16 - 30 31 - 45 46 - 60 61 - 75 76 - 90 1 - 15 91 - 105 106 - 120 17 - 32 33 - 48 49 - 64 65 - 80 81 - 96 1 - 16 97 - 112 113 - 128 18 - 34 35 - 51 52 - 68 69 - 85 86 - 102 1 - 17 103 - 119 120 - 136 figure 4. offset registers serial bit sequence
23 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges if the queue is full, the first read operation will cause ff to go high after two wclks. subsequent read operations will cause paf to go high at the conditions described in table ?. if further read operations occur, without write operations, pae will go low when there are n words in the queue, where n is the empty offset value. continuing read operations will cause the queue to become empty. then the last word has been read from the queue, the ef will go low inhibiting further read operations. ren is ignored when the queue is empty. when configured in idt standard mode, the ef and ff outputs are double register-buffered outputs. idt standard mode is available when the device is configured in both single data rate and double data rate mode. relevant timing diagrams for idt standard mode can be found in figures 14, 15, 16. first word fall through mode (fwft) in this mode, the status flags or , ir , pae , and paf operate in the manner outlined in table 4. to write data into to the queue, wcs must be low. data presented to the data in lines will be clocked into the queue on subsequent transitions of wclk. after the first write is performed, the output ready ( or ) flag will go lowafter 3rd rising edge of rclk. subsequent writes will continue to fill up the queue. pae will go high after n + 2 words have been loaded into the queue, where n is the empty offset value. the default setting for these values are listed in table 4. this parameter is also user programmable as described in the serial writing and reading of offset registers section. continuing to write data into the queue without performing read operations will cause the programmable almost-full flag ( paf ) to go low. again, if no reads are performed, the paf will go low after (8,193-m) writes for the idt72t55248, (16,385-m) writes for the idt72t55258, and (32,769-m) writes for the idt72t55268. this is assuming the i/o bus width is configured to x40. if the i/o is x20, then paf will go low after (16,385-m) writes for the idt72t55248, (32,769-m) writes for the idt72t55258, and (65,537-m) writes for the idt72t55268. if the i/o is x10, then paf will go low after (32,769-m) writes for the idt72t55248, (65,537-m) writes for the idt72t55258, and (131,073-m) writes for the idt72t55268. the offset ?m? is the full offset value. the default setting for these values are listed in table ?. this parameter is also user programmable. see the section on serial writing and reading of offset registers for details. when the queue is full, the input ready ( ir ) will go low, inhibiting further write operations. if no reads are performed after a reset, ir will go low after d writes to the queue. if the i/o bus width is configured to x40, then d = 8,193 writes for the idt72t55248, 16,385 writes for the idt72t55258, and 32,769 writes for the idt72t55268. if the i/o is x20, then d = 16,385 writes for the idt72t55248, 32,769 writes for the idt72t55258, and 65,537 writes for the idt72t55268. if the i/o is x10, then d = 32,769 writes for the idt72t55248, 65,537 writes for the idt72t55258, and 131,073 writes for the idt72t55268. if the queue is full, the first read operation will cause ir to go high after two wclks after rclk. subsequent read operations will cause paf to go high at the conditions described in table ? if further read operations occur, without write operations, pae will go low when there are n words in the queue, where n is the empty offset value. continuing read operations will cause the queue to become empty. then the last word has been read from the queue, the or will go high inhibiting further read operations. rcs is ignored when the queue is empty. when configured in fwft mode, the or flag output is triple register-buffered and the ir flag output is double register-buffered. relevant timing diagrams for fwft mode can be found in figures 17, 18, 19. 6157 drwsft 0 1 to n (1) (n+1) to (8,192 - m) 8,192 f f p a f p a e e f hhl l hhl h hlhh llhh idt72t55248 idt72t55258 idt72t55258 idt72t55248 idt72t55248 ow = x20 number of words in queue ow = x10 idt72t55268 ow = x40 idt72t55268 idt72t55258 idt72t55268 0 1 to n (1) (n+1) to (16,384 - m) 16,384 0 1 to n (1) (n+1) to (32,768 - m) 32,768 0 1 to n (1) (n+1) to (65,536 - m) 65,536 0 1 to n (1) (n+1) to (131,072 - m) 131,072 0 1 to n+1 (1) (n+2) to (8,193 - m) 8,193 f f p a f p a e e f hhl l hhl h hlhh llhh idt72t55248 idt72t55258 idt72t55258 idt72t55248 idt72t55248 ow = x20 number of words in queue ow = x10 idt72t55268 ow = x40 idt72t55268 idt72t55258 idt72t55268 0 1 to n+1 (1) (n+2) to (16,385 - m) 16,385 0 1 to n+1 (1) (n+2) to (32,769 - m) 32,769 0 1 to n+1 (1) (n+2) to (65,537 - m) 65,537 0 1 to n+1 (1) (n+2) to (131,073 - m) 131,073 note: 1. n, m = 7 if fsel[1:0] = 00, n, m = 63 if fsel[1:0] = 01, n, m = 127 if fsel[1:0] = 10, n, m = 1023 if fsel[1:0] = 11. note: 1. n, m = 7 if fsel[1:0] = 00, n, m = 63 if fsel[1:0] = 01, n, m = 127 if fsel[1:0] = 10, n, m = 1023 if fsel[1:0] = 11. table 3 status flags for idt standard mode table 4 status flags for fwft mode
24 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges hstl/lvttl i/o the inputs and outputs of this device can be configured for either lvttl or hstl/ehstl operation. if the iosel pin is high during master reset, then all applicable lvttl or hstl signals will be configured for hstl/ehstl operating voltage levels. to select between hstl or ehstl v ref must be driven to 0.75v or 0.9v respectively. typically a logic high in hstl would be v ref 300mv and a logic low would be v ref 300mv. if the iosel pin is low during master reset, then all applicable lvttl or hstl signals will be configured for lvttl operating voltage levels. in this configuration v ref must be set to the static core voltage of 2.5v. table ? illustrates which pins are and are not associated with this feature. note that all ?static pins? must be tied to v cc or gnd. these pins are cmos only and are purely device configuration pins. note the iosel pin should be tied high or low and cannot toggle before and after master reset. bus matching the write and read port has bus-matching capability such that the input and output bus can be either 10 bits, 20 bits or 40 bits wide, depending on which operating mode the device is configured to. the bus width of both the input and output port is determined during master reset using the input and output width setup pins (iw[1:0], ow[1:0]). the selected port width is applied to all four queue ports, such that all four queues will be configured for either x10, x20 or x40 bus widths. when writing or reading data from a queue the number of memory locations available to be written or read will depend on the bus width selected and the density of the device. if the write/read port is 10 bits wide, this provides the user with a queue depth of 32,768 x 10 for the idt72t55248, 65,536 x 10 for the idt72t55258, or 131,072 x 10 for the idt72t55268. if the write/read port is 20 bits wide, this provides the user with a queue depth of 16,384 x 20 for the idt72t55248, 32,768 x 20 for the idt72t55258, or 65,536 x 20 for the idt72t55268. if the write/read port is 40 bits wide, this provides the user with a queue depth of 8,192 x 40 for the idt72t55248, 16,384 x 40 for the idt72t55258, or 32,768 x 40 for the idt72t55268. the queue depths will always have a fixed density of 327,680 bits for the idt72t55248, 655,360 bits for the idt72t55258 and 1,310,072 bits for the idt72t55268 regardless of bus-width configuration on the write/read port. when the device is operating in double data rate, the word is twice as large as in single data rate since one word written or read on both the rising and falling edge of clock. therefore in ddr, the queue depths will be half of what it is mentioned above. for instance, if the write/read port is 10 bits wide, the depth of each queue is 16,384 x 10 for the idt72t55248, 32,768 x 10 for the idt72t55258, or 65,536 x 10 for the idt72t55268. see figure 5, bus-matching byte arrangement for more information. lvttl/hstl/ehstl static cmos signals write port read port jtag control pins serial port static pins d[39:0] cef / cor tck fsel[1:0] sclk iosel wclk0/1/2/3 ef 0/1/2/3 trst is[1:0] sren iw[1:0] wen 0/1/2/3 or 0/1/2/3 tms os[1:0] swen md[1:0] ff 0/1/2/3 erclk0/1/2/3 tdi pd fwft/si ow[1:0] wcs 0/1/2/3 oe 0/1/2/3 tdo mrs sdo pfm cff / cir pae 0/1/2/3 prs 0/1/2/3 rddr paf 0/1/2/3 q[39:0] fwft/si wddr rclk0/1/2/3 rcs 0/1/2/3 ren 0/1/2/3 eren [3:0] table 5 i/o voltage level associations
25 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 5. bus-matching byte arrangement (mux mode) 6157 drw09 x10 input to x40 output for queue0 2nd: write to queues l os1 os0 ow1 lh byte order on output port: d39-d30 d29-d20 d19-d10 d9-d0 a 1st: write to queues mux mode byte order on input port: b 4th: write to queues c 3rd: write to queues d queue0 q39-q30 q29-q20 q19-q10 q9-q0 a 1st: read from queues b c d 1st: read from queues a c 2nd: read from queues x10 input to x20 output for queue0 2nd: read from queues a 1st: read from queues b 4th: read from queues c 3rd: read from queues d x10 input to x10 output for queue0 ow0 l b d l os1 os0 ow1 ll byte order on output port: ow0 h l os1 os0 ow1 ll ow0 l byte order on output port: q39-q30 q29-q20 q19-q10 q9-q0 q39-q30 q29-q20 q19-q10 q9-q0 queue1 queue2 queue3 notes: = high-z outputs. = inputs set to gnd.
26 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 5. bus-matching byte arrangement (demux mode) (continued) 6157 drw10 x40 input to x10 output for queue1 1st: read from queues d39-d30 d29-d20 d19-d10 d9-d0 a 1st: write to queues a 3rd: read from queues b 2nd: read from queues c 1st: write to queues a x20 input to x10 output for queue1 x10 input to x10 output for queue1 b lhl h l is1 is0 iw1 hh iw0 l 4th: read from queues d is1 is0 iw1 iw0 1st: read from queues a 2nd: read from queues b 1st: write to queues a 1st: read from queues a lhl l is1 is0 iw1 iw0 demux mode byte order on input port: byte order on input port: byte order on input port: x b c d q39-q30 q29-q20 q19-q10 q9-q0 x x x x x x x x x x x note: x is data in the output register. d39-d30 d29-d20 d19-d10 d9-d0 q39-q30 q29-q20 q19-q10 q9-q0 q39-q30 q29-q20 q19-q10 qn-q0 d39-d30 d29-d20 d19-d10 d9-d0 queue0 queue1 queue2 queue3 x x x x x x x x x
27 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 5. bus-matching byte arrangement (broadcast mode) (continued) 6157 drw11 x40 input to x10 output for every queue 1st: read from queues a 1st: write to queues broadcast mode byte order on input port: 3rd: read from queues b 2nd: read from queues c 1st: write to queues a x20 input to x10 output for every queue x10 input to x10 output to every queue b 4th: read from queues d 1st: read from queues 2nd: read from queues 1st: write to queues a 1st: read from queues l l iw1 iw0 a a a a b b b b c c c c d d d d a a a a b b b b a a a a l h iw1 iw0 h l iw1 iw0 byte order on input port: byte order on input port: d39-d30 d29-d20 d19-d10 d9-d0 q39-q30 q29-q20 q19-q10 q9-q0 d39-d30 d29-d20 d19-d10 d9-d0 q39-q30 q29-q20 q19-q10 q9-q0 d39-d30 d29-d20 d19-d10 d9-d0 q39-q30 q29-q20 q19-q10 q9-q0
28 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges selectable modes the device is capable of operating in three different modes, mux, demux, and broadcast write. each of these three modes can be selected based on the md[1:0] bits. these bits should be tied directly to v cc or gnd as they are latched in during master reset. the state of the md pins for each mode is summarized in table 1 ? device configuration. each mode has access to four dedicated queues internally, with each queue having densities of 327,680 bits for the idt72t55248, 655,360 bits for the idt72t55258 and 1,310,072 bits for the idt72t55268. the density of each queue is fixed and cannot be programmed. also, the density does not change when the device is operating in single or double data rate, or when the device is utilizing the bus-matching feature. the quadmux flow-control device accommodates for all of the timing issues associated with converging multiple data rates onto one path. such issues include clock skew, race conditions, and meeting setup and hold times. these issues are difficult to address when performing mux operations from external logic or within an fpga, especially at higher frequencies. the complexity of the design makes it difficult to implement within an fpga, where speed degradations occur as the circuit becomes more complicated. mux mode in mux mode the device is configured as shown in the mux mode block diagram on page 1. the device in this mode consists of four separate queues: queue 0, queue 1, queue 2 and queue 3. the four queues all have the same common read port, and the read control selecting which queue to read from. the mux mode can be used in applications where multiple incoming data rates from different data paths are being buffered to one common data rate and data bus. write port operation in mux mode there are four independent write port controls for each individual queue. data can be written to any of the four queues using its corresponding write clock, write enable, and write chip select. a data word will be written on the rising (and falling in ddr) edge of write clock provided wen and write chip select are active. note in double data rate the setup and hold times of the write enables and write chip selects are sampled with respect to the rising edge of its respective write clock only. the falling edge of wclk does not sample the write enable and write chip select. in fwft mode the first word written to any queue will automatically be placed onto the output bus of that respective queue when selected on the read port via the os[1:0] pins. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. this is regardless of the state of the corresponding read enable and read chip select, provided that the selected queue was empty. this is not true in idt standard mode, where the first word written to a selected queue must be accessed by setting ren and rcs are low on the rising edge of rclk. read port operation in mux mode the output select pins (os[1:0]) determine which one of the four queues the output bus will read data from. the output select pins are sampled on the rising edge of every rclk, and may change on every clock edge. thus there is no latency switching from one queue to another. note that in mux mode only the rclk0 is active, all other output read clocks are not used. the same applies to the read enable ( ren 0) and read chip select ( rcs 0). data will be read on the rising (and falling in ddr) edge of read clock provided read enable and read chip select are active (low). when selecting a queue for read operations the new word read from that queue will be available immediately on the next clock edge after the new queue is selected. for example, if os[1:0] is set to 01 (queue1) on rclk edge 0, then on rclk edge 1 (next read clock edge) data can be read from queue1 if ren 0 and rcs 0 are enabled. in fwft mode, the first word written to a selected queue will automatically be placed onto the output bus of that respective queue regardless of the state of the corresponding read enable, provided that the selected queue was empty and its corresponding output ready flag was inactive. this occurs due to the nature of the fwft flag timing. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. subsequent writes to the queue that is not empty will not fall through to the output bus. note in fwft mode, during a queue selection the next word available in the queue will automatically fall through to the output bus regardless of the read enable and read chip select. in idt standard mode, every word including the first word must be accessed by the read enable and read chip select. unlike fwft mode, during a queue selection the next word available in the queue will not automatically fall through to the output bus. the previous word that was read out of the read port will remain on the output bus if the ren and rcs select are high. demux mode in demux mode the device is configured as shown in the demux mode block diagram on page 2. the device in this mode consists of four separate queues: queue 0, queue 1, queue 2 and queue 3. the four queues all have the same common write port, and the read control selecting which queue to read from. the demux mode can be used in applications where a single incoming data rate is being buffered to multiple outgoing data rates. write port operation in demux mode the input select pins (is[1:0]) determine which one of the four queues the input bus will write data into. the input select pins are sampled on the rising edge of every wclk, and may change on every clock edge. thus there is no latency switching from one queue to another. note that in demux mode only the wclk0 is active, all other input write clocks are not used. the same applies to the write enable ( wen 0) and write chip select ( wcs 0). data will be written on the rising (and falling in ddr) edge of write clock provided wen and wcs are active on the rising edge of the wclk. note in double data rate the setup and hold times of the wen and wcs selects are sampled with respect to the rising edge of the write clock only. the falling edge of wclk does not sample the write enable and write chip select. when selecting a queue for write operations the next word can be written to that queue immediately on the next clock edge after the new queue is selected. for example, if is[1:0] is set to 01 (queue1) on wclk edge 0, then on wclk edge 1 (next read clock edge) data can be written to queue1 if wen 0 and wcs 0 are enabled. in fwft mode the first word written to a selected queue will automatically be placed onto the output bus regardless of the state of the corresponding read enable, provided that the selected queue was empty and its corresponding output ready flag was inactive. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. this occurs due to the nature of the fwft flag timing. subsequent writes to the queue that is not empty will not fall through to the output bus. in idt standard mode, every word including the first word must be accessed by the read enable and read chip select. read port operation in demux mode there are four independent read port controls for each individual queue. data can be read from any of the four queues using its
29 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges corresponding read clock, read enable, and read chip select. a data word will be read on the rising (and falling in ddr) edge of read clock provided read enable and read chip select are active. there are also four individual output enables that will take the output bus to high-impedance. note that data will be read from memory regardless of the state of the output enable oe [3:0] pins. as explained above, in fwft mode the first word written to each queue will automatically be placed onto the output bus regardless of the of the state of the corresponding read enable. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. broadcast write mode in broadcast write mode the device is configured as shown in the broadcast write mode block diagram on page 2. the device in this mode consists of four separate queues: queue 0, queue 1, queue 2 and queue 3. the four queues all have one common write port which will write data into all four queues simultaneously when a write operation is initiated, there is no write selection to write data into a specific queue. the broadcast write mode can be used in applications where a single incoming data bus needs to be sent to multiple data paths simultaneously. write port operation in broadcast write mode there are no input or output select pins to select the individual queues separately. the write port will write data into all four queues simultaneously. note that in broadcast mode only the wclk0 is active, all other input clocks are not used. the same applies to the write enable ( wen 0) and write chip select ( wcs 0). data will be written on the rising (and falling in ddr) edge of write clock provided write enable and write chip select are active (low) on the rising edge of write clock. write operations are prohibited if any of the four queues are being partially reset or any of their full flag status full ( ff = low). in fwft mode, the first word written to a selected queue will automatically be placed onto the output bus of that respective queue regardless of the state of the corresponding read enable, provided that the selected queue was empty and its corresponding output ready flag was inactive. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. this occurs due to the nature of the fwft flag timing. subsequent writes to the queue that is not empty will not fall through to the output bus. in idt standard mode, every word including the first word must be accessed by the read enable and read chip select. read port operation in broadcast write mode there are four independent read port controls for each individual queue. data can be read from any of the four queues using its corresponding read clock, read enable, and read chip select. a data word will be read on the rising (and falling in ddr) edge of read clock provided read enable and read chip select are active. there are also four individual output enables that will take the output bus to high-impedance. note that data will be read from memory regardless of the state of the output enable oe [3:0] pins.
30 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges signal descriptions inputs: data input bus (d[39:0]) the data input bus can be 40, 20, or 10 bits wide in demux and broadcast mode. d[39:0] are data inputs for the 40-bit wide data bus, d[19:0] are data inputs for 20-bit wide data bus, and d[9:0] are data inputs for the 10-bit wide data bus. in mux mode the input bus will be 10 bits wide for each of the four internal queues. d[9:0] are dedicated to queue 0, d[19:10] are dedicated to queue 1, d[29:20] are dedicated to queue 2, and d[39:30] are dedicated to queue 3. data can be written into each of the four queues on every wclk cycle. there is a two cycle input pipeline and a two cycle output pipeline. it will take two cycles or three rising edges of the wclk to move data from the write port to the queue and two cycles or those rising edges of rclk to move data from the queue to the data outlines. master reset ( mrs ) there is a single master reset available for all internal queues in this device. a master reset is accomplished whenever the mrs input is taken to a low state. this operation sets the internal read and write pointers of all queues to the first location in memory. the programmable almost empty flag will go low and the almost full flags will go high. if fwft/si signal is low during master reset then idt standard mode is selected. this mode utilizes the empty and full status flags from the ef / or and ff / ir dual-purpose pin. during master reset, all empty flags will be set to low and all full flags will be set to high. if fwft/si signal is high during master reset, then the first word fall through mode is selected. this mode utilizes the input read and output ready status flags from the ef / or and ff / ir dual-purpose pin. during master reset, all input ready flags will be set to low and all output ready flags will be set to high. all device configuration pins such as md[1:0], ow[1:0], iw[1:0], is[1:0], os[1:0], wddr, rddr, iosel, pfm, fsel[1:0] and fwft/si needs to be defined before the master reset cycle. during a master reset the output register is initialized to all zeros. if the output enable(s) are low during master reset, then the output bus will be low. if the output enable(s) are high during master reset, then the output bus will be in high-impedance. rcs has no affect on the data outputs during master reset. if the output width ow[1:0] is configured to x10 or x20, then the unused outputs will be in high-impedance. a master reset is required after power up before a write operation to any queue can take place. master reset is an asynchronous signal and thus the read and write clocks can be free-running or idle during master reset. see figure 10, master reset timing , for the associated timing diagram. partial reset ( prs 0/1/2/3) a partial reset is a means by which the user can reset both the read and write pointers of each individual queue inside the device without changing the queue?s configuration. there are four dedicated partial reset signals that each correspond to an i ndividual queue. there are restrictions as to when partial reset can be performed that apply to each operating modes. in mux mode, partial reset may not be performed on the two queues involved during queue selection on the read port. for instance, if os[1:0] is switching from 00 to 01 then prs 0 and prs 1 may not be enabled from the first rising rclk edge with os[1:0]=01 until three more rising rclk edges have been received. in other words, partial reset may not be performed for a minimum of three rclk cycles from the time a new queue is selected. also, if queue0 or queue1 are partially reset before the switch, the appropriate prs signal must return high at least t rsr (reset recovery time) before the first rclk edge with os[1:0]=01. any queues not involved in the selection can be partially reset. in demux mode, partial reset may not be performed on the two queues involved during queue selection on the write port. for instance, if is[1:0] is switching from 11 to 10 then prs 3 and prs 2 may not be enabled from the first rising wclk edge with os[1:0]=01 until three more rising wclk edges have been received. in other words, partial reset may not be performed for a minimum of three wclk cycles from the time a new queue is selected. also, if queue0 or queue1 are partially reset before the switch, the appropriate prs signal must be high at least t rsr (reset recovery time) before the first wclk edge with is[1:0]=10. any queues not involved in the selection can be partially reset. in broadcast mode, partial reset may not be performed during write operations. the write enable and write chip select must be high with respect to the rising edge of wclk0 for a minimum of t rss before partial reset can be performed. if the device is operating in ddr mode, partial reset of any queue must be initiated after the falling edge of wclk0 to ensure data from the falling edge are written into all four queues in memory. this maintains the data integrity of all four queues in the device. see figures 11, 12, 13, partial reset timing , for the associated timing diagram. first word fall through/serial in (fwft/si) this is a dual purpose pin. during master reset, the state of the fwft/si input determines whether the device will operate in idt standard mode or first word fall through (fwft) mode. if fwft/si is low before the falling edge of master reset, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the queues memory. it also uses the full flag function ( ff ) to indicate whether or not the queues memory has any free space for writing. in idt standard mode, every word read from the queues, including the first, must be requested using the read enable ( ren ), read chip select ( rcs ) and rclk. if fwft/si is high before the falling edge of master reset, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (qn). it also uses input ready ( ir ) to indicate whether or not the queues have any free space for writing. in the fwft mode, the first word written to an empty queue goes directly to qn after three rclk rising edges, provided that the first rclk meets t skew param- eters. there will be a one rclk cycle delay if t skew is not met. ren and rcs do not need to be enabled. subsequent words must be accessed using the ren , rcs , and rclk. rcs must be low or the outputs will be in a high- state. the state of the fwft/si input must be kept at the present state for the minimum of the reset recovery time (t rsr ) after master reset. after this time, the fwft/si acts as a serial input for loading pae and paf offsets into the programmable offset registers. the serial input is used in conjunction with sclk, swen , sren , and sdo to access the offset registers. serial program- ming using the fwft/si pin functions the same way in both idt standard and fwft modes. write clock (wclk0/1/2/3) there are a possible total of four write clocks available in this device depending on the mode selected, each corresponding to the individual queues in memory. a write cycle is initiated on the rising and/or falling edge of the wclk input. if the write double data rate (wddr) mode pin is tied high during master reset, data will be written on both the rising and falling edge of wclk0/1/2/3, provided that wen 0/1/2/3 and wcs 0/1/2/3 are enabled. if wddr is tied low, data will be written only on the rising edge of wclk0/1/2/3 provided that wen 0/ 1/2/3 and wcs 0/1/2/3 are enabled. the four write clocks are completely independent of one another.
31 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges data setup and hold times must be met with respect to the low-to-high (and high-to-low in ddr) transition of the write clock(s). it is permissible to stop the write clock(s). note that while the write clocks are idle, the ff / ir 0/1/2/3 and paf 0/1/2/3 flags will not be updated unless it is operating in asynchronous timing mode (pfm=00). the write clocks can either be independent or coincident of one another. in demux and broadcast write mode, only the wclk0 input is available. all other write clocks inputs should be tied to gnd. write enable ( wen 0/1/2/3) there are a possible total of four write enables available in this device depending on the mode selected, one for each individual queues in memory. when the write enable input is low on the rising edge of wclk in single data rate, data is loaded on the rising edge of every wclk cycle, provided the device is not full and the write chip select ( wcs ) is enabled. the setup and hold times are referenced with respect to the rising edge of wclk only. when the write enable input is low on the rising edge of wclk in double data rate, data is loaded into the selected queue on the rising and falling edge of every wclk cycle, provided the device is not full and the write chip select ( wcs ) is enabled. in this mode, the data setup and hold times are referenced with respect to the rising and falling edge of wclk. note that wen and wcs are sampled only on the rising edge of wclk in either data rate modes. data is stored in the queues sequentially and independently of any ongoing read operation. when the write enable(s) and write chip select(s) are high, no new data is written into the corresponding queue on each wclk cycle. the four write enables operate independent of one another. in demux and broadcast mode, only the wen 0 input is available. all other write enables should be tied to v cc . write chip select ( wcs 0/1/2/3) there are a possible total of four write chip selects available in this device depending on the mode selected, one for each individual queues in memory. the write chip selects disables all write port inputs for each individual queue if it is held high. to perform normal write operations for each individual queue, the write chip select must be enabled, held low. the four write chip selects are completely independent of one another. when the write chip select is low on the rising edge of wclk in single data rate, data is loaded on the rising edge of every wclk cycle, provided the device is not full and the write enable ( wen ) of the corresponding queue is low. when the write chip select is low on the rising edge of wclk in double data rate, data is loaded into the selected queue on the rising and falling edge of every wclk cycle, provided the device is not full and the write enable ( wen ) of the corresponding queue is low. when the write chip select is high on the rising edge of wclk in single data rate, the write port is disabled and no words are written on the rising edge of wclk into the queue, even if wen is low. if the write chip select is high on the rising edge of wclk in double data rate, the write port is also disabled and no words are written on the rising and falling edge of wclk into the queue, even if wen is low. note that wcs is sampled on the rising edge of wclk only in either data rate modes. in demux and broadcast mode, only the wcs 0 input is available. all other write chip selects should be tied to v cc . write double data rate (wddr) when the write double data rate (wddr) pin is high prior to master reset, the write port will be set to double data rate mode. in this mode, all write operations are based on the rising and falling edge of the write clocks, provided that write enables and write chip selects are low for the rising clock edges. in double data rate the write enable signals are sampled with respect to the rising edge of write clock only, and a word will be written on both the rising and falling edge of write clock regardless of whether or not the write enables are active on the falling edge of write clock. when wddr is low, the write port will be set to single data rate mode. in this mode, all write operations are based on only the rising edge of the write clocks, provided that write enables and write chip selects are low during the rising edge of write clock. this pin should be tied high or low and cannot toggle before or after master reset. read clock (rclk0/1/2/3) there are a possible total of four read clocks available in this device depending on the mode selected, each corresponding to the individual queues in memory. a read cycle is initiated on the rising and/or falling edge of the rclk input. if the read double data rate (rddr) mode pin is tied high, data will be read on both the rising and falling edge of rclk0/1/2/3, provided that ren 0/ 1/2/3 and rcs 0/1/2/3 are enabled. if rddr is tied low, data will be read only on the rising edge of rclk0/1/2/3 provided that ren 0/1/2/3 and rcs 0/ 1/2/3 are enabled. the four read clocks are completely independent of one another. there is an associated data access time (t a ) for the data to be read out of the queues. it is permissible to stop the read clocks. note that while the read clocks are idle, the ef / or 0/1/2/3 and pae 0/1/2/3 flags will not be updated unless it is operating in asynchronous timing mode (pfm=0). the write and read clocks can either be independent or coincident. in mux mode, only the rclk0 input is available. all other read clock inputs should be tied to gnd. read enable ( ren 0/1/2/3) there are a possible total of four read enables available in this device depending on the mode selected, one for each individual queue in memory. when the read enable input is low on the rising edge of rclk in single data rate, data will be read on the rising edge of every rclk cycle, provided the device is not empty and the read chip select ( rcs ) is enabled. the associated data access time (ta) is referenced with respect to the rising edge of rclk. when the read enable input is low on the rising edge of rclk in double data rate, will be read on the rising and falling edge of every rclk cycle, provided the device is not empty and rcs is enabled. in this mode, the data access times are referenced with respect to the rising and falling edges of rclk. note that ren is sampled only on the rising edge of rclk in either data rate modes. data is stored in the queues sequentially and independently of any ongoing write operation. when the read enable(s) and read chip select(s) are high, no new data is read on each rclk cycle. the four read enables operate independent of one another. to prevent reading from an empty queue in the idt standard mode, the empty flag of each queue will go low with respect to rclk, when the total number of words in the queue has been read out, thus inhibiting further read operations. upon the completion of a valid write cycle, the empty flag will go high with respect to rclk two cycles later, thus allowing another read to occur, providing t skew of wclk to rclk is met. in mux mode, only the ren 0 input is available. all other read enables should be tied to v cc . read chip select ( rcs 0/1/2/3) there are a possible total of four read chip selects available in this device, each corresponding to the individual queue in memory. the read chip select inputs provides synchronous control of the read port for each individual queue. when the read chip select is held low, the next rising edge of the correspond-
32 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges ing rclk will enable the output bus. when the read chip select goes high, the next rising edge of rclk will send the output bus into high-impedance and prevent that rclk from initiating a read, regardless of the state of ren . during a master or partial reset the read chip select input has no effect on the output bus, output enable ( oe [3:0]) is the only input that provides high-impedance control of the output bus. if output enable is low, the data outputs will be active regardless of read chip select until the first rising edge of rclk after a reset is complete. afterwards if read chip select is high the data outputs will go to high- impedance. the four read chip selects are completely independent of one another. the read chip select inputs do not affect the updating of the flags. for example, when the first word is written to any/all empty queues, the empty flag(s) will still go from low to high based on a rising edge of the rclk(s), regardless of the state of the read chip select inputs. also, when operating the queue in fwft mode the first word written to any/all empty queues will still be clocked through to the output bus on the third rising edge of rclk(s), regardless of the state of read chip select inputs, assuming that the t skew parameter is met. for this reason the user should pay extra attention to the read chip selects when a data word is written to any/all empty queues in fwft mode. if the read chip select inputs are high when an empty queue is written into, the first word will fall through to the output register but will not be available on the outputs because they are in high-impedance. the user must enable the read chip selects on the next rising edge of rclk to access this first word. in mux mode, only the rcs 0 input is available. all other read chip select inputs should be tied to v cc . read double data rate (rddr) when the read double data rate (rddr) pin tied high, the read port will be set to double data rate mode, sampled during master reset. in this mode, all read operations are based on the rising and falling edge of the read clocks, provided that read enables and read chip selects are low. in double data rate mode, the read enable signals are sampled with respect to the rising edge of read clock only, and a word will be read from both the rising and falling edge of read clock regardless of whether or not read enable and read chip select are active on the falling edge of read clock. when rddr is tied low at master reset, the read port will be set to single data rate mode. in this mode, all read operations are based on only the rising edge of the read clocks, provided that read enables and read chip selects are low during the rising edge of read clock. this pin should be tied high or low and cannot toggle before and after master reset. output enable ( oe 0/1/2/3) there are a possible total of four asynchronous output enables available in this device, each corresponding to the individual queues in memory. when the output enable inputs are low, the output bus of each individual queue become active and drives the data currently in the output register. when the output enable inputs ( oe [3:0]) are high, the output bus of each individual queue goes into high-impedance. during master or partial reset the output enable is the only input that can place the output data bus into high-impedance. during reset the read chip select input has no effect on the output data bus. the four output enable inputs are completely independent of one another. in mux mode, only the oe 0 input is available. all other output enable inputs should be tied to gnd. i/o select (iosel) the inputs and outputs of this device can be configured for either lvttl or hstl/ehstl operation. if the iosel pin is high during master reset, then all applicable lvttl or hstl signals will be configured for hstl/ehstl operating voltage levels. to select between hstl or ehstl vref must be driven to 0.75v or 0.9v respectively. if the iosel pin is low during master reset, then all applicable lvttl or hstl signals will be configured for lvttl operating voltage levels. in this configuration vref should be set to the static core voltage of 2.5v. this pin should be tied high or low and cannot toggle before or after master reset. please refer to table ? for a list of applicable lvttl/hstl/ehstl signals. power down ( pd ) this device has a power down feature intended for reducing power consumption for hstl/ehstl configured inputs when the device is idle for a long period of time. by entering the power down state certain inputs can be disabled, thereby significantly reducing the power consumption of the part. all wen and ren signals must be disabled for a minimum of four wclk and rclk cycles before activating the power down signal. the power down signal is asynchronous and needs to be held low throughout the desired power down time. during power down, the following conditions for the inputs/outputs signals are: ? all data in queue(s) are retained. ? all data inputs become inactive. ? all write and read pointers maintain their last value before power down. ? all enables, chip selects, and clock input pins become inactive. ? ? ? ? ? all data outputs become inactive and enter high-impedance state. ? ? ? ? ? all flag outputs will maintain their current states before power down. ? ? ? ? ? all programmable flag offsets maintain their values. ? ? ? ? ? all echo clocks and enables will become inactive and enter high-impedance state. ? ? ? ? ? the serial programming and jtag port will become inactive and enter high-impedance state. ? ? ? ? ? all setup and configuration cmos static inputs are not affected, as these pins are tied to a known value and do not toggle during operation. all internal counters, registers, and flags will remain unchanged and maintain their current state prior to power down. clock inputs can be continuous and free- running during power down, but will have no affect on the part. however, it is recommended that the clock inputs be low when the power down is active. to exit power down state and resume normal operations, disable the power down signal by bringing it high. there must be a minimum of 1 s waiting period before read and write operations can resume. the device will continue from where it had stopped, no form of reset is required after exiting power down state. the power down feature does not provide any power savings when the inputs are configured for lvttl operation. however, it will reduce the current for i/os that are not tied directly to v cc or gnd. see figure ?, for the associated timing diagram. serial clock (sclk) the serial clock is used to load data and read data from in the programmable offset registers. data from the serial input signal (fwft/si) can be loaded into the offset registers on the rising edge of sclk provided that the serial write enable ( swen ) signal is low. data can be read from the offset registers via the serial data output (sdo) signal on the rising edge of sclk provided that sren is low. the serial clock can operate at a maximum frequency of 10mhz. the read operation is non-destructive. however, the write operation will change the flag offsets on each sclk rising edge as data shifts into the registers. serial write enable ( swen ) the serial write enable input is an enable used for serial programming of the programmable offset registers. it is used in conjunction with the serial input
33 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges (fwft/si) and serial clock (sclk) when programming the offset registers. when the serial write enable is low, data at the serial input is loaded into the offset register, one bit for each low-to-high transition of sclk. when serial write enable is high, the offset registers retain the previous settings and no offsets are loaded. serial write enable functions the same way in both idt standard and fwft modes. serial read enable ( sren ) the serial read enable input is an enable used for reading the value of the programmable offset registers. it is used in conjunction with the serial data output (sdo) and serial clock (sclk) when reading the offset registers. when the serial read enable is low, data at the serial data output can be read from the offset register, one bit for each low-to-high transition of sclk. when serial read enable is high, the reading of the offset registers will stop. whenever serial read enable ( sren ) is activated values in the offset registers are read starting from the first location in the offset registers. the sren high to low transition copies the values in the offset registers directly into a serial scan out register. sren must be kept low in order to read the entire contents of the offset register. if at any point sren is toggled high to low, another copy function from the offset register to the serial scan out register will occur. serial read enable functions the same way in both idt standard and fwft modes. outputs: data output bus (q[39:0]) the data output bus can be 40, 20, or 10 bits wide in mux mode. q[39:0] are data outputs for the 40-bit wide data bus, q[19:0] are data outputs for 20-bit wide data bus, and q[9:0] are data outputs for the 10-bit wide data bus. in demux and broadcast mode the output bus will be 10 bits wide for each of the four internal queues. q[9:0] are dedicated to queue 0, q[19:10] are dedicated to queue 1, q[29:20] are dedicated to queue 2, and q[39:30] are dedicated to queue 3. in fwft mode, when switching from one queue to another, the data of the newly selected queue will always be present on the output bus two cycles after the next rclk cycle after os[1:0] is selected providing rcs is low regardless of whether or not ren is active. thus each of the four queues can be accessed on every rclk cycle. empty/output ready flag ( ef / or 0/1/2/3) there are four empty/output ready flags available in this device, each corresponding to the individual queues in memory. this is a dual-purpose pin that is determined based on the state of the fwft/si pin during master reset for selecting one of the two timing modes of this device. in the idt standard mode, the empty flags are selected. when an individual queue is empty, its empty flag will go low, inhibiting further read operations from that queue. when the empty flag is high, the individual queue is not empty and valid read operations can be applied. see figures 24, 25, read cycle, empty flag and first word latency timing (idt standard mode), for the relevant timing information. also see table 3 ?status flags for idt standard mode? for the truth table of the empty flags. in fwft mode, the output ready flags are selected. output ready flags ( or ) go low at the same time that the first word written to an empty queue appears on the outputs, which is a minimum of three read clock cycles provided the rclk and wclk meets the t skew parameter. or stays low after the rclk low- to-high transitions that shifts the last word from the queue to the outputs. or goes high when an enabled read operation is performed to an empty queue. the previous data stays at the outputs, indicating the last word was read. further data reads are inhibited until a new word is on the bus when or goes low again. see figures 21, 22, 23, read timing (fwft mode ), for the relevant timing information. also see table 4 ?status flags for fwft mode? for the truth table of the empty flags. the empty/output ready flags are synchronous and updated on the rising edge of rclk. in idt standard mode, the flags are double register-buffered outputs. in fwft mode, the flags are triple register-buffered outputs. the four empty flags operate independent of one another and always indicate the respective queue?s status. composite empty/output ready flag ( cef / cor ) this status pin is used to determine the empty state of the current queue selected. the composite empty/output ready flag represents the state of the queue selected on the read port, such that the user does not have to monitor each individual queues? empty/output ready flags. the composite empty/output ready flag is only available in mux mode, since the output select bits (os[1:0]) are used to select any one of the four queues to read from. the timing of the composite empty/output ready flag differs in idt standard and fwft modes. in idt standard mode, when switching from one queue to another, the composite empty flag will update to the status of the newly selected queue one rclk cycle after the rising edge of rclk that made the new queue selection. in fwft mode, the composite output ready flag will update to the status of the newly selected queue on two clock cycles after the rising edge of rclk that made the new queue selection. see figures 26, 27 for the associated timing diagram. see table 3 and 4 ?status flags for idt standard and fwft mode ? for the truth table of the composite empty flag. full/input ready flag ( ff / ir 0/1/2/3) there are four full/input ready flags available in this device, each corresponding to the individual queues in memory. this is a dual-purpose pin that is determined based on the state of the fwft/si pin during master reset for selecting the two timing modes of this device. in the idt standard mode, the full flags are selected. when an individual queue is full, its full flags will go low after the rising edge of wclk that wrote the last word, thus inhibiting further write operations to the queue. when the full flag is high, the individual queue is not full and valid write operations can be applied. see figures 14, 15, 16, write cycle, full flag and first word latency timing (idt standard mode), for the associated timing diagram. also see table 3 ?status flags for idt standard mode? for the truth table of the full flags. in fwft mode, the input ready flags are selected. input ready flags go low when there is adequate memory space in the queues for writing in data. the input ready flags go high after the rising edge of wclk that wrote the last word, when there are no free spaces available for writing in data. see figures 17, 18, 19, write timing (fwft mode ), for the associated timing information. also see table 4 ?status flags for fwft mode? for the truth table of the full flags. the input ready status not only measures the depth of the queues memory, but also counts the presence of a word in the output register. thus, in fwft mode, the total number of writes necessary to make ir high is one greater than needed to set ff = low in idt standard mode. in broadcast mode, when any one of the four full flags becomes asserted, all write operations to every queue will be disabled. this maintains data integrity throughout all four queues for comparison. in all other modes, the full flag will only disable write operations to its corresponding queue. ff / ir is synchronous and updated on the rising edge of wclk. ff / ir are double register-buffered outputs. the four full flags operate independent of one another, except in broadcast mode. to prevent data overflow in the idt standard mode, the full flag of each queue will go low with respect to wclk, when the maximum number of words has been written into the queue, thus inhibiting further write operations. upon the
34 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges completion of a valid read cycle, the full flag will go high with respect to wclk two cycles later, thus allowing another write to occur, provided t skew has been met. to prevent data overflow in the fwft mode, the input ready flag of each queue will go high with respect to wclk, when the maximum number of words has been written into the queue, thus inhibiting further write operations. upon the completion of a valid read cycle, the input ready flag will go low with respect to wclk two cycles later, thus allowing another write to occur, provided t skew has been met. composite full/input ready flag ( cff / cir ) this status pin is used to determine the full state of the current queue selected. the composite full/input ready flag represents the state of the queue selected on the write port, such that the user does not have to monitor each individual queues? full/input ready flags. the composite full/input ready flag is only available in both demux and broadcast modes. when switching from one queue to another, the composite full/input ready flag will update to the status of the newly selected queue one wclk cycle after the rising edge of wclk that made the new queue selection, regardless of which timing mode the device is operating in. see figure ? for the relevant associated timing diagram. see table ? and ? ?status flags for idt standard and fwft mode ? for the truth table of the composite full flag programmable almost empty flag ( pae 0/1/2/3) there are four programmable almost empty flags available in this device, each corresponding to the individual queues in memory. the programmable almost empty flag is an additional status flag that notifies the user when the queue is near empty. the user may utilize this feature as an early indicator as to when the queue will become empty. in idt standard mode, pae will go low when there are n words or less in the queue. in fwft mode, the pae will go low when there are n-1 words or less in the queue. the offset ?n? is the empty offset value. the default setting for this value is stated in table ?. since there are four internal queues hence four pae offset values, n0, n1, n2, and n3. there are two timing modes available for the pae flags, selectable by the state of the programmable flag mode (pfm) pin during master reset. if pfm is tied high, then synchronous timing mode is selected. if pfm is tied low, then asynchronous timing mode is selected. in synchronous pae configuration, the pae flag is updated on the rising edge of rclk. in asynchronous pae configuration, the pae flag is asserted low on the low-to-high transitions of the read clock (rclk). pae is reset to high on the low-to-high transitions of the write clock (wclk). see figure ? and ?, synchronous and asynchronous programmable almost-empty flag timing (idt standard and fwft mode), for the relevant timing information. the four programmable almost empty flags operate independent of one another. programmable almost full flag ( paf 0/1/2/3) there are four programmable almost full flags available in this device, each corresponding to the individual queues in memory. the programmable almost full flag is an additional status flag that notifies the user when the queue is nearly full. the user may utilize this feature as an early indicator as to when the queue will not be able to accept any more data and thus prevent data from being dropped. in idt standard mode, if no reads are performed after master reset, paf will go low after (d-m) (d meaning the density of the particular device) words are written to the queue. in fwft mode, paf will go low after (d+1- m) words are written to the queue. the offset ?m? is the full offset value. the default setting for this value is stated in table 2. since there are four internal queues hence four paf offset values, m0, m1, m2, and m3. there are two timing modes available for the paf flags, selectable by the state of the programmable flag mode (pfm) pin during master reset. if pfm is tied high, then synchronous timing mode is selected. if pfm is tied low, then asynchronous timing mode is selected. in synchronous paf configuration, the paf flag is updated on the rising edge of wclk. in asynchronous paf configuration, the paf flag is asserted low on the low-to-high transitions of the write clock (wclk). paf is reset to high on the low-to-high transitions of the read clock (rclk). see figures 35 and 37, synchronous and asynchronous programmable almost-full flag timing (idt standard and fwft mode), for the relevant timing information. the four programmable almost full flags operate independent of one another. table 6 t skew measurement data port status flags t skew measurement datasheet configuration parameter ddr input ef / or negative edge wclk to t skew2 to positive edge rclk ddr output ff / ir negative edge rclk to t skew2 positive edge wclk pae negative edge wclk to t skew3 positive edge rclk paf negative edge rclk to t skew3 positive edge wclk ddr input ef / or negative edge wclk to t skew2 to positive edge rclk sdr output ff / ir positive edge rclk to t skew1 positive edge wclk pae negative edge wclk to t skew3 positive edge rclk paf positive edge rclk to t skew3 positive edge wclk sdr input ef / or positive edge wclk to t skew1 to positive edge rclk ddr output ff / ir negative edge rclk to t skew2 positive edge wclk pae positive edge wclk to t skew3 positive edge rclk paf negative edge rclk to t skew3 positive edge wclk sdr input ef / or positive edge wclk to t skew1 to positive edge rclk sdr output ff / ir positive edge rclk to t skew1 positive edge wclk pae positive edge wclk to t skew3 positive edge rclk paf positive edge rclk to t skew3 positive edge wclk
35 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges echo read clock (erclk0/1/2/3) there are four echo read clock outputs available in this device, each corresponding to their respective input read clocks in the queue. the echo read clock is a free-running clock output, that will always follow the rclk input regardless of the read enables and read chip selects. the erclk output follows the rclk input with an associated delay. this delay provides the user with a more effective read clock source when reading data from the output bus. this is especially helpful at high speeds when variables within the device may cause changes in the data access times. these variations in access time may be caused by ambient temperature, supply voltage, or device characteristics. any variations effecting the data access time will also have a corresponding effect on the echo read clock output produced by the device, therefore the echo read clock output level transitions should always be at the same position in time relative to the data outputs. note, that echo read clock is guaranteed by design to be slower than the slowest data outputs. refer to figure 6, echo read clock and data output relationship , figure 27, echo read clock and read enable operation in double data rate mode and figure 28, echo rclk and echo ren operation for timing information. the four echo read clock outputs operate independent of one another and are direct copies of their respective rclk inputs. echo read enable ( eren 0/1/2/3) there are four echo read enable outputs available in this device, each corresponding to the individual queues in memory. the echo read enable output is provided to be used in conjunction with the echo read clock and provides the device receiving data from the queue with a more effective scheme for reading the queues? data. the echo read enable output is controlled by internal logic that becomes active for the read clock cycle that a new word is read out of the queue. that is, a rising edge of read clock will cause echo read enable to go low, if both read enable and read chip select are active and the queue is not empty. in other words, every cycle puts data on the output bus and drives eren output to the low. figure 6. echo read clock and data output relationship notes: 1. ren is low. oe is low. 2. t erclk > t a , guaranteed by design. 3. qslowest is the data output with the slowest access time, t a . 4. time, t d is greater than zero, guaranteed by design. 5. ddr mode clocks data on rising and falling edge of rclk. 6157 drw12 erclk t a t d q slowest (3) rclk t erclk t a (5)
36 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges tdo tdo tdi/ tms tck trst t doh notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = trst (reset pulse width) t4 = trsr (reset recovery) 6157 drw13 t 3 t 4 t 1 t 2 t tck t dh t ds t do figure 7. standard jtag timing note: 1. 50pf loading on external output signals. system interface parameters idt72t55248 idt72t55258 idt72t55268 parameter symbol test conditions min. max. units data output t do (1) -20ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 - parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag reset t rst -50-ns jtag reset recovery t rsr -50-ns jtag ac electrical characteristics (v cc = 2.5v 5%; tambient (industrial) = 0 c to +85 c)
37 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges jtag timing specifications (ieee 1149.1 compliant) the jtag test port in this device is fully compliant with the ieee standard test access port (ieee 1149.1) specifications. five additional pins (tdi, tdo, tms, tck and trst ) are provided to support the jtag boundary scan interface. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of seven basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) ? bypass register (byr) ? id code register ? flag programming the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 8. jtag architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal jtag state machine. it consists of four input ports (tclk, tms, tdi, trst ) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and updating of data passed through the tdi serial input. in pad in pad incell incell core logic outcell outcell out pad out pad all outputs all inputs eg: dins, clks (bsdl file describes the chain order) id bypass instruction register ta p tms tdi tck trst instruction select enable tdo 6157 drw14 flag offset chain
38 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. the tap controller takes precedence over the queue operation and must be reset after power up of the device. see trst description for more details on tap controller reset. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test-logic-reset state can be entered by holding tms at high and pulsing tck five times. this is the reason why the test reset ( trst ) pin is optional. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idle otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state other wise. figure 9. tap controller state diagram capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tck. the last two significant bits are always required to be ?01?. shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tck. the instruction available on the tdi pin is also shifted in to the instruction register. tdo changes on the falling edge of tck. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register scan chain is latched in to the register of the instruction register on every falling edge of tck. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tck. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path. test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 6157 drw15 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input is tms 0 0 1 notes: 1. five consecutive 1's at tms will reset the tap. 2. tap controller resets automatically upon power-up.
39 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges the instruction register the instruction register (ir) is eight bits long and tells the device what instruction is to be executed. information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during capture-dr. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in the serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary-scan register (bsr) is 48 bits long. it contains one boundary-scan cell (bsc) for each normal-function input pin and one bsc for each normal-function i/o pin (one single cell for both input data and output data). the bsr is used 1) to store test data that is to be applied externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the device to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the idt72t55248/72t55258/72t55268, the part number field con- tains the following values: idt72t55248/258/268 jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0000 0033 (hex) 1 jtag instruction register the instruction register allows an instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e. ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. hex instruction function value 0000 extest test external pins 0001 sample/preload select boundary scan register 0002 idcode selects chip identification register 0003 clamp fix the output chains to scan chain values 0004 high-impedance puts all outputs in high-impedance state 0007 offset read read pae / paf offset register values 0008 offset write write pae / paf offset register values 000f bypass select bypass register private several combinations are private (for idt internal use). do not use codes other than those identified above. jtag instruction register decoding the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the required extest instruction places the device into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. as such, the extest instruction is the workhorse of ieee. std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. sample/preload the required sample/preload instruction allows the device to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the device. this instruction is also used to preload test data into the boundary-scan register before loading an extest instruction. idcode the optional idcode instruction allows the device to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the device manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the device. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power- up of the device or after the tap has been reset using the optional trst pin or by otherwise moving to the test-logic-reset state. device part# field idt72t55248 04c9 (hex) idt72t55258 04ca (hex) idt72t55268 04cb (hex)
40 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges clamp the optional clamp instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the one- bit bypass register to be connected between tdi and tdo. before loading this instruction, the contents of the boundary-scan register can be preset with the sample/preload instruction. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the outputs. high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an device to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the device outputs. offset read this instruction is an alternative to serial reading the offset registers for the pae / paf flags. when reading the offset registers through this instruction, the dedicated serial programming signals must be disabled. offset write this instruction is an alternative to serial programming the offset registers for the pae / paf flags. when writing the offset registers through this instruction, the dedicated serial programming signals must be disabled. bypass the required bypass instruction allows the device to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the device.
41 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges ef / or 0/1/2/3 t rsf if fwft = high, or = high if fwft = low, ef = low t rsf paf 0/1/2/3 t rsf t rsf q[39-0] t rsf oe = high oe = low 6157 drw16 ow[1:0] (4) , iw[1:0] (4) fsel[1:0] (4) pfm (4) high = synchronous pae / paf timing low = asynchronous pae / paf timing md[1:0] (4) t rss high = fwft mode low = idt standard mode rddr (4) , wddr (4) fwft/si (4) iosel (4) high = read/write double data rate low = read/write single data rate high = hstl i/os low = lvttl i/os t rss t rss t rss t rss t rss t rss if fwft = low, ff = high if fwft = high, ir = low ff / ir 0/1/2/3 pae 0/1/2/3 is[1:0] (4) , os[1:0] (4) t rss t rs mrs wen ren t rss swen , sren t rss t rsr t rsr figure 10 . master reset notes: 1. oe can be toggled during this period. 2. prs should be high during a mrs . 3. rclk(s), wclk(s) and sclk(s) can be free running or idle. 4. the state of these pins are latched when the master reset pulse is low. 5. jtag clock should not toggle during master reset. 6. rcs and wcs can be high or low until the first rising edge of rclk after master reset is complete. 7. eren wave form is identical to ren , erclk wave form is identical to rclk.
42 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges wen 0/1, ren 0/1 t rss prs 2/3 (1) 6157 drw17 ff / ir 0/1 t rsf current state current state ff / ir 2/3 t rsf if fwft = high, ff = high if fwft = low, ir = low if fwft = high, cff = high if fwft = low, cir = low pae 0/1 t rsf current state pae 2/3 t rsf paf 0/1 t rsf current state paf 2/3 t rsf q[39-0] (2,4) t rsf oe = high oe = low current state current state t rss t rsr wen 2/3, ren 2/3 t rss t rsr os[1:0] t ens 00 = queue 0 01 = queue 1 ef / or 0/1 t rsf current state current state ef / or 2/3 t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = high, or = high if fwft = low, ef = low rclk0 123 prs 0/1 (1) t rs t rs cef / cor t rsf current state if fwft = high, cor = high if fwft = low, cef = low 4 output data queue 0 output data queue 1 figure 11 . partial reset for mux mode notes: 1. during the output selection of two queues, partial reset of the two queues involved are prohibited. 2. during partial reset the high-impedance control of the output is provided by oe only. 3. prs 0/1 must go low after the fourth rising edge of rclk0. 4. this is the output data from queue0 and queue1.
43 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges wen 0, ren 0/1 t rss prs 2/3 (1) 6157 drw18 current state t rsf if fwft = high, ff = high if fwft = low, ir = low t rsf current state pae 2/3 t rsf paf 0/1 t rsf current state paf 2/3 t rsf q[9-0] (2,4) q[19-10] (2,5) t rsf oe = high oe = low current state current state t rss t rsr ren 2/3 t rss t rsr is[1:0] t ds 00 = queue 0 01 = queue 1 ef / or 0/1 t rsf current state current state ef / or 2/3 t rsf if fwft = high, or = high if fwft = low, ef = low if fwft = high, or = high if fwft = low, ef = low ff / ir 0/1 t rsf current state ff / ir 2/3 if fwft = high, ff = high if fwft = low, ir = low pae 0/1 wclk0 123 prs 0/1 (1) t rs t rs 4 cff / cir t rsf current state if fwft = high, ff = high if fwft = low, ir = low q[29-20] (2,6) q[39-30] (2,7) t rsf oe = high oe = low figure 12 . partial reset for demux mode notes: 1. during the output selection of two queues, partial reset of the two queues involved are prohibited. 2. during partial reset the high-impedance control of the output is provided by oe only. 3. prs 0/1 must go low after the fourth rising edge of wclk0. 4. this is the output data from queue0. 5. this is the output data from queue1. 6. this is the output data from queue2. 7. this is the output data from queue3.
44 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 13. partial reset for broadcast mode wclk0 ren (2) 0/1/2/3 t rss prs 0/1/2/3 6157 drw19 (1) wen 0 ef / or 0/1/2/3 t rsf if fwft = high, or = high if fwft = low, ef = low t rss ff / ir 0/1/2/3 t rsf if fwft = low, ff = high if fwft = high, ir = low pae 0/1/2/3 t rsf paf 0/1/2/3 t rsf q[39-0] (3,4) t rsf oe = high oe = low cff / cir t rsf if fwft = low, ff = high if fwft = high, ir = low notes: 1. if the write port is configured in double data rate, partial reset must be initiated after the falling edge of wclk0 to ensur e falling edge data is written into memory. 2. only the read enable of the queue involved in partial reset need to be high. 3. during partial reset the high-impedance control of the outputs is provided by oe only. 4. only affects the output of the queue partial reset is applied to.
45 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 14. write cycle and full flag timing (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out os[1:0] 00=queue 0 t a previous word+1 queue 0 6157 drw20 12 rclk0 3 ren 0 01=queue 1 q[39:0] (4) previous word queue 0 t a word 0 queue 1 t a word 0 queue 2 t a word 1 queue 2 t a t ens t ens t enh 10=queue 2 wclk1 wen 0 12 d[9:0] t skew (3) t ens no write w d-1 wclk0 no write no write wen 1 ff 0 t wff t wff ff 1 t dh t ds w d d[19:10] w d-1 t ds t ds w d t dh t dh t enh t enh t wff t wff t dh t skew (2) notes: 1. wcs 0, wcs 1 are low. 2. this is the skew between rclk0 and wclk0 for queue0. 3. this is the skew between rclk0 and wclk1 for queue1. 4. there is a two-stage pipeline so each read appears in the data bus two cycles or three rising edges of rclk later.
46 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk2 t skew1 din[9:0] wen 0 no write wclk0 no write t ens t dh word d t dh t ds word d-1 word d+1 t dh t ds word d+2 word 1 q[29:20] 6157 drwa t a previous data in output register ff 2 t wff t wff t wff t wff ff 1 t wff ff 0 t skew1 ren 2 t ens rclk1 ren 1 t ens rclk0 ren 0 t ens t a word 2 t a word 3 t a word 4 t a word 5 t a word 6 t a word 7 word 1 t a t a word 2 t a word 3 t a word 4 q[19:10] previous data in output register word 1 t a q[9:0] previous data in output register 12 12 figure 15. write cycle and full flag timing (broadcast write mode, idt standard mode, sdr to sdr) x10 in to x10 out note: 1. wcs 0, rcs 0/1/2, and oe 0/1/2 are low.
47 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk2 t skew1 din[9:0] (2) t dh word x queue x t dh t ds word x-1 queue x q[29:20] 6157 drwb previous data in output register ff 2 t wff t wff t wff t wff ff 1 ff 0 ren 2 t ens rclk1 ren 1 t ens rclk0 ren 0 t ens t a word 1 t a word 2 t a word 3 t a word 4 t a word 5 word 2 t a t a word 3 t a word 4 q[19:10] previous data in output register q[9:0] previous data in output register wen 0 wclk0 no write 10 = queue 2 is[1:0] 01 = queue 1 00 = queue 0 10 01 00 t enh t ens 10 01 word 0 queue 2 word 0 queue 1 t wff t wff t skew1 t skew1 word 1 t a word 2 t a t a word 3 word 1 t a t enh 12 12 word 1 queue 1 word 0 queue 0 figure 16. write cycle and full flag timing (demux mode, idt standard mode, sdr to sdr) x10 in to x10 out notes: 1. wcs 0, rcs 0/1/2, and oe 0/1/2 are low. 2. there is a two-stage pipeline so each read appears in the queue two cycles or three rising edges of wclk later.
48 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk0 t skew1 word 1 q[9:0] 6157 drwc t a previous data in output register t a word 2 t a word 3 word 4 q[19:10] ren 0 t ens or 0 t wff or 1 din[9:0] wen 0 wclk0 t ens word 2 t dh t ds word 1 t enh word 3 word 4 d[19:10] wen 1 wclk1 t ens word 2 t dh t ds word 1 t enh word 3 word 4 12 3 00 = queue 0 os[1:0] 01 = queue 1 t ens word 1 t a previous data in output register word 2 t a t dh t dh figure 17. write timing (mux mode, fwft mode, sdr to sdr) x10 in to x10 out note: 1. wcs 0/1, and oe 0/1 are low.
49 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk3 t skew1 word 1 q[39:30] 6157 drwd t a previous data in output register t a word 2 t a word 3 word 4 q[9:0] ren 3 t ens 12 3 word 1 t a previous data in output register word 2 t a or 3 t ref or 0 din[9:0] wen 0 wclk0 t ens word 2 t dh t ds word 1 word 3 word 4 word 5 word 6 word 7 t ref rclk0 t skew1 ren 0 t ens 12 3 t a figure 18. write timing (broadcast write mode, fwft mode, sdr to sdr) x10 in to x10 out note: 1. wcs 0, rcs 0/3, and oe 0/3 are low.
50 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk2 t skew1 6157 drwe word 2 t a word 3 t a q[29:20] previous data in output register q[19:10] previous data in output register word 1 t a word 2 t a t a word 3 word 1 t a ren 2 rclk1 ren 1 12 3 din[9:0] (2) or 2 or 1 t ens wen 0 wclk0 10 = queue 2 is[1:0] 01 = queue 1 10 01 10 01 t ens 10 01 t ref word x queue x t dh t ds t enh word 0 queue 2 word 0 queue 1 word 1 queue 2 word 1 queue 1 word 2 queue 2 word 2 queue 1 t ref t skew1 12 3 figure 19. write timing (demux mode, fwft mode, sdr to sdr) x10 in to x10 out notes: 1. wcs 0, rcs 1/2, and oe 1/2 are low. 2. there is a two-stage pipeline so each read appears in the queue two cycles or three rising edges of wclk later.
51 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk0 ren 0 12 ef t ref t ref t ref wen 3 d[39:30] q[39:0] t ens wx-3 t a no read no read wx-1 t a wx cef t ref t ref t ref wclk3 t skew t ens t enh t dh wx (byte 0) 6157 drw22 t a wx-2 t ds t ds t dh wx (byte 1) t ds t dh wx (byte 2) t ds t dh wx (byte 3) figure 20. read cycle, empty flag and first word latency (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out notes: 1. rcs 0, wcs 3, oe 3 are low. 2. os[1:0] = 11. 3. wx (byte 0) = q[9:0], wx (byte 1) = q[19:10], wx (byte 2) = q[29:20], wx (byte 3) = q[39:30].
52 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk1 t skew1 6157 drwf w4 t a q[19:10] w1 w2 t a ren 1 12 din[9:0] ir 0 wen 0 wclk0 w d t dh t ds t wff t wff w3 t a rclk0 w2 q[9:0] w1 ren 0 t a t ref t ref figure 21. read timing (broadcast write mode, fwft mode, sdr to sdr) x10 in to x10 out notes: 1. wcs 0, rcs 0/1, and oe 0/1 are low. 2. q[39:10] = 0.
53 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk0 6157 drwg w4 t a q[9:0] w1 w2 t a ren 0 ir 0 t wff t wff w3 t a t ens t skew1 12 d[9:0] wen 0 wclk0 w d t enh t ens t a w5 6157 drwh t a w1 byte d t a t ens t a rclk0 q[9:0] ren 0 ir 0 t wff t wff t skew1 12 d[19:0] wen 0 wclk0 w d t enh t ens t dh t ds w1 byte 1 w2 byte d w2 byte 1 figure 23. read timing (demux mode, fwft mode, sdr to sdr) x20 in to x10 out notes: 1. wcs 0, rcs 0, and oe 0 are low. 2. is[1:0] = 00. q[39:10] = 0. 3. w d is a 20-bit word. q[9:0] = byte 0, q[19:10] = byte 1. figure 22. read timing (mux mode, fwft mode, sdr to sdr) x10 in to x10 out notes: 1. wcs 0, rcs 0, and oe 0 are low. 2. os[1:0] = 00. 3. q[39:10] = 0.
54 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk0 ren 0 ef 1 q[19:10] wclk0 wen 0 d[19:0] is[1:0] ren 1 rclk1 ef 0 q[9:0] t skew1 12 t ref 6157 drwi previous data in output register t a w x byte 0 t a 01 = queue 1 00 = queue 0 01 t ens t enh wx byte 0 - byte 1 t ds t ens t skew1 12 w x byte 1 t ens t ref previous data in output register t a w x byte 0 t a w x byte 1 t ens t ens t dh wx byte 0 - byte 1 t ds t dh figure 24. read cycle, empty flag and first word latency (demux mode, idt standard mode, sdr to sdr) x20 in to x10 out notes: 1. wcs 0, rcs 0/1, and oe 0/1 are low. 2. w x is a 20-bit word. lsb = byte 0, msb = byte 1.
55 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges rclk1 ren 1 ef 2 q[29:20] wclk0 wen 0 d[39:0] 6157 drwj wx byte 0 - byte 3 t ds t dh ren 2 rclk2 ef 1 q[19:10] t skew1 12 t ref previous data in output register t a w x byte 0 t a t ens 12 w x byte 3 t ens t ref previous data in output register t a w x byte 0 t a w x byte 1 t ens t ref t a w x byte 2 t a w x byte 1 t a t ens no read figure 25. read cycle, empty flag and first word latency (broadcast write mode, idt standard mode, sdr to sdr) x40 in to x10 ou t notes: 1. wcs 0, rcs 1/2, and oe 1/2 are low. 2. w x is a 40-bit word. lsb = byte 0-byte 1, msb = byte 2-byte 3.
56 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges ren 0 ef rclk0 t a 6157 drw23 12 3 q[39:0] (3) word d-1 queue 1 os[1:0] 01 = queue 1 11 = queue 3 word d queue 1 t ens t a next word queue 3 t ref cef t ref t ref no read t ds figure 26. composite empty flag (mux mode, idt standard mode, sdr to sdr) x10 in to x40 out notes: 1. rcs 0 and oe 0 are low. 2. ef 3 is high. 3. word d-1 is the second and last word in queue 1. word d is the last word in queue 1. ren 0 or 1 rclk0 t a 6157 drw24 12 3 q[39:0] (3) word d-1 queue 1 os[1:0] 01 = queue 1 11 = queue 3 word d queue 1 t ens t ens t a next word queue 3 t ref cor t ref t ref figure 27. composite output ready flag (mux mode, fwft mode, sdr to sdr) x10 in to x40 out notes: 1. rcs 0 and oe 0 are low. 2. or 3 is low. 3. word d-1 is the second and last word in queue 1. word d is the last word in queue 1.
57 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges wen 0 wclk0 6157 drw25 cff t wff t wff 12 3 is[1:0] 01 = queue 1 11 = queue 3 t ens no write d[19:0] word d queue 1 t ds t dh t dh word d queue 3 word d+1 queue 3 ff t wff t ds t dh t ds figure 28. composite full flag (demux mode, idt standard mode, sdr to sdr) x20 in to x10 out notes: 1. wcs 0 is low. 2. ff 3 is high. wen 0 wclk0 6157 drw26 cir t wff 12 3 is[1:0] t ens no write d[19:10] (3) t dh ir 1 t wff word d+1 queue 1 t ds t dh word d queue 3 word d+1 queue 3 01 = queue 1 11 = queue 3 t ds t dh t ds t wff figure 29. composite input ready flag (demux mode, fwft mode, sdr to sdr) x20 in to x10 out notes: 1. wcs 0 is low. 2. ir 3 is low. 3. word d is the first word written and fell through to output (fwft).
58 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 30. echo read clock and read enable operation (mux/demux/broadcast mode, idt standard mode, ddr to ddr) x10 in to x10 o ut notes: 1. the eren 0 output is ?or gated? to rcs 0 and ren 0 and will follow these inputs provided that the queue is not empty. if the queue is empty, eren 0 will go high to indicate that there is no new word available. 2. the eren 0 output is synchronous to rclk0. 3. oe 0 = low, wddr = high, and rddr = high. 4. q[39:10] = 0. 5. the truth table for eren is shown below: rclk0 ren 0 eren 0 erclk0 ef 0 rcs 0 t ens t ref t erclk t enh q[9:0] t ens t enh t clken t clken t clken t clken t olz t a t a t clken t a t olz t olz t a t a t a t a t a w d-10 w d-9 w d-8 w d-6 w d-5 w d-4 w d-3 w d-2 last word w d 6157 drw27 t clken t a w d-7 w d-6 t a w d-1 t ens no read no read rclk ef rcs ren eren 1000 1011 1101 1111 0xx1
59 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 31. echo rclk and echo read enable operation (mux/demux/broadcast mode, fwft mode, sdr to sdr) note: 1. the o/p register is the internal output register. its contents are available on the qn output bus only when rcs0 and oe 0 are both active, low, that is the bus is not in high-impedance state. 2. oe 0 is low. 3. q[39:10] = 0. cycle: a&b. at this point the queue is empty, or 0 is high. rcs 0 and ren 0 are both disabled, the output bus is high-impedance. c. word wn+1 falls through to the output register, or 0 goes active, low. rcs 0 is high, therefore the qn outputs are high-impedance. eren 0 goes low to indicate that a new word has been placed into the output register. d. eren 0 goes high, no new word has been placed on the output register into this cycle. e. no operation. f. rcs 0 is low on this cycle, therefore the qn outputs go to low-impedance and the contents of the output register (wn+1) are made av ailable. note: in fwft mode it is important to take rcs 0 active low at least one cycle ahead of ren 0, this ensures the word (wn+1) currently in the output register is made available for at least one cycle, otherwise wn+1 will overwritten by wn+2. g. ren 0 goes active low, this reads out the second word, wn+2. eren 0 goes active low to indicate a new word has been placed into the output register. h. word wn+3 is read out, eren 0 remains active, low indicating a new word has been read out. note: wn+3 is the last word in the queue. i. this is the next enabled read after the last word, wn+3 has been read out. or 0 flag goes high and eren0 goes high to indicate that there is no new word available. 4. oe 0 is low, wddr = low, and rddr = low. 5. the truth table for eren is shown below: q[9:0] o/p (1) reg. t a t ref or 0 6157 drw28 t rcslz ren 0 t ens t enh rcs 0 t ens rclk0 a b c d e f g h i w n+1 wclk0 wen 0 d[9:0] t skew1 t ens t ds t enh w n+2 w n+3 erclk0 eren 0 t clken t clken t clken t clken w n+1 w n+2 w n+3 t a t ref w n+1 w n+2 w n+3 w n last word t dh t dh t dh t ds t ds 1 2 t erclk high-z t enh rclk or rcs ren eren 0000 0011 0101 0111 1xx1
60 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges 6157 drw29 rclk0 ren 0 t erclk erclk0 rcs 0 t ens eren 0 t clken t clken t clken ef 0 t ref q[9:0] t olz t a t a t a t a t a w d-1 w d last word w d-2 w d-3 w d-4 figure 32. echo read clock and read enable operation (mux/demux/broadcast mode, idt standard mode, sdr to sdr) x10 in to x10 o ut notes: 1. the eren 0 output is ?or gated? to rcs 0 and ren 0 and will follow these inputs provided that the queue is not empty. if the queue is empty, eren 0 will go high to indicate that there is no new word available. 2. the eren 0 output is synchronous to rclk0. 3. oe 0 = low, wddr = high, and rddr = high. 4. q[39:10] = 0. 5. the truth table for eren is shown below: rclk ef rcs ren eren 1000 1011 1101 1111 0xx1
61 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 33. loading of programmable flag registers (idt standard and fwft modes) t senh t sdh sclk swen fwft/si 6157 drw30 empty offset 3 full offset 3 t sens t sds bit x (1) 8 bit 1 t scl k t sckh t sckl bit 1 (lsb) empty offset 0 full offset 0 bit 1 bit 1 (lsb) bit x (1) 8 bit x (1) 8 bit x (1) 8 (msb) (msb) figure 34. reading of programmable flag registers (idt standard and fwft modes) sclk sren sdo 6157 drw31 empty offset 3 full offset 3 t sens t soa t sen h bit x (1) t senh t sclk t sckh t sckl bit 0 bit 0 bit x (1) bit x (1) t soa bit 0 empty offset 0 full offset 0 bit 0 (lsb) bit x (1) (msb) (lsb) (msb) note: 1. if iw/ow = x40, x = 104 for the idt72t55248, x = 112 for the idt72t55258, x = 120 for the idt72t55268. if iw/ow = x20, x = 112 for the idt72t55248, x = 120 for the idt72t55258, x = 128 for the idt72t55268. if iw/ow = x10, x = 120 for the idt72t55248, x = 128 for the idt72t55258, x = 136 for the idt72t55268. note: 1. if iw/ow = x40, x = 104 for the idt72t55248, x = 112 for the idt72t55258, x = 120 for the idt72t55268. if iw/ow = x20, x = 112 for the idt72t55248, x = 120 for the idt72t55258, x = 128 for the idt72t55268. if iw/ow = x10, x = 120 for the idt72t55248, x = 128 for the idt72t55258, x = 136 for the idt72t55268.
62 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges wclk wen 0 paf 0 rclk0 ren 0 6157 drw32 1 2 12 d - m0 words in queue (1) d - (m0 +1) words in queue (1) t enh t ens t pafs t ens t enh t clkl t skew2 (3) t pafs t clkl wclk0 wen 0 pae 0 rclk0 12 12 ren 0 6157 drw33 n0 words in queue t ens t skew2 (4) t enh t paes n0 + 1 words in queue (2) , n0 + 2 words in queue (3) t ens t enh t clkh t clkl notes: 1. m0 = paf 0 offset . 2. d = maximum queue depth. for density of queue with bus-matching, refer to the bus-matching section on page 19. 3. t skew2 is the minimum time between a rising rclk0 edge and a rising wclk0 edge to guarantee that paf 0 will go high (after one wclk0 cycle plus t pafs ). if the time between the rising edge of rclk0 and the rising edge of wclk0 is less than t skew2 , then the paf 0 deassertion time may be delayed one extra wclk0 cycle. 4. paf 0 is asserted and updated on the rising edge of wclk0 only. 5. select this mode by setting pfm high during master reset. 6. rcs 0 = low, wcs 0 = low, wddr = low, and rddr = low. figure 35. synchronous programmable almost-full flag timing (mux/demux/broadcast mode, idt standard and fwft mode, sdr to sdr) x10 in to x10 out notes: 1. the timing diagram shown is for queue0. queues1-3 exhibit the same behavior. 2. n0 = pae 0 offset. 3. for idt standard mode 4. for fwft mode. 5. t skew2 is the minimum time between a rising wclk0 edge and a rising rclk0 edge to guarantee that pae 0 will go high (after one rclk0 cycle plus t paes ). if the time between the rising edge of wclk0 and the rising edge of rclk0 is less than t skew2 , then the pae 0 deassertion may be delayed one extra rclk0 cycle. 6. pae 0 is asserted and updated on the rising edge of wclk0 only. 7. select this mode by setting pfm high during master reset. 8. rcs 0 = low, wcs 0 = low, wddr = low, and rddr = low. figure 36. synchronous programmable almost-empty flag timing (mux/demux/broadcast mode, idt standard and fwft mode, sdr to sdr) x10 in to x10 out
63 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges wclk0 wen 0 paf 0 d - (m0 + 1) words in queue rclk0 t pafa ren 0 6157 drw34 d - m0 words in queue d - (m0 + 1) words in queue t ens t pafa t enh t ens t clkl t clkh wclk0 wen 0 pae 0 n0 words in queue (2) , n0 + 1 words in queue (3) rclk0 ren 0 6157 drw35 t paea n0 + 1 words in queue (2) , n 0+ 2 words in queue (3) t paea t ens t ens t enh t clkl t clkh n0 words in queue (2) , n0 + 1 words in queue (3) notes: 1. m0 = paf 0 offset. 2. d = maximum queue depth. for density of queue with bus-matching, refer to the bus-matching section on page 19. 3. paf 0 is asserted to low on wclk0 transition and reset to high on rclk0 transition. 4. select this mode by setting pfm low during master reset. 5. rcs 0 is low, wcs 0 is low, wddr = low, and rddr = low. figure 37. asynchronous programmable almost-full flag timing (mux/demux/broadcast mode, idt standard and fwft mode, sdr to sdr) x10 in to x10 out notes: 1. n0 = pae 0 offset. 2. for idt standard mode. 3. for fwft mode. 4. pae 0 is asserted low on rclk0 transition and reset to high on wclk0 transition. 5. select this mode by setting pfm low during master reset. 6. rcs 0 is low, wcs 0 is low, wddr = low, and rddr = low. figure 38. asynchronous programmable almost-empty flag timing (mux/demux/broadcast mode, idt standard and fwft mode, sdr to sdr) x10 in to x10 out
64 idt72t55248/72t55258/72t55268 2.5v quadmux ddr flow-control device with mux/demux/broadcast functions 8k x 40 x 4, 16k x 40 x 4 and 32k x 40 x 4 commercial and industrial temperature ranges figure 39. power down operation 6157 drw36 wclk wen d[39:0] t ds t dh t dh w d10 w d11 t ds t dh t ds w d13 rclk ren t a t a t a t erclk t pdhz (7) t pdlz (2) t pdl t pdh (2) t pdh (2) w dh (8) hi-z hi-z w d4 w d3 w d2 w d1 hi-z t eren q[39:0] pd erclk eren 12 3 4 (1) t ds 1 s t a t eren w ds w d12 notes: 1. all read and write operations must have ceased a minimum of 4 wclk and 4 rclk cycles before power down is asserted. 2. when the pd input becomes deasserted, there will be a 1 s waiting period before read and write operations can resume. all input and output signals will also resume after this time period. 3. set-up and configuration static inputs are not affected during power down. 4. serial programming and jtag programming port are inactive during power down. 5. rcs = 0, wcs = 0 and oe = 0. these signals can toggle during and after power down. 6. all flags remain active and maintain their current states. 7. during power down, all outputs will be in high-impedance.
65 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1533 santa clara, ca 95054 fax: 408-492-8674 email: flow-controlhelp@idt.com www.idt.com plastic ball grid array (pbga, bb324-1) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 6157 drwlast commercial and industrial commercial and industrial idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72t55248 8,192 x 40 x 4 ? 2.5v quadmux ddr flow-control device 72t55258 16,384 x 40 x 4 ? 2.5v quadmux ddr flow-control device 72t55268 32,768 x 40 x 4 ? 2.5v quadmux ddr flow-control device clock cycle time (t clk ) speed in nanoseconds bb 5 6-7 l ordering information datasheet document history 12/01/2003 pgs. 1, 8, 17, and 36.

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